diff options
| author | Anton Korobeynikov <asl@math.spbu.ru> | 2009-07-16 14:12:54 +0000 |
|---|---|---|
| committer | Anton Korobeynikov <asl@math.spbu.ru> | 2009-07-16 14:12:54 +0000 |
| commit | 54cea741ca45264ee2d08c48093620389e788c96 (patch) | |
| tree | fef1470303b3ff38fc938252476061f0fe3bd130 /lib/Target/SystemZ/SystemZInstrInfo.cpp | |
| parent | c3a5196133ff15d95bb01510ae2386ba1a528668 (diff) | |
Add proper register aliases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75999 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/SystemZ/SystemZInstrInfo.cpp')
| -rw-r--r-- | lib/Target/SystemZ/SystemZInstrInfo.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/SystemZ/SystemZInstrInfo.cpp b/lib/Target/SystemZ/SystemZInstrInfo.cpp index c82aa0b9b4..92418ac11f 100644 --- a/lib/Target/SystemZ/SystemZInstrInfo.cpp +++ b/lib/Target/SystemZ/SystemZInstrInfo.cpp @@ -149,8 +149,6 @@ bool SystemZInstrInfo::isMoveInstr(const MachineInstr& MI, unsigned &SrcReg, unsigned &DstReg, unsigned &SrcSubIdx, unsigned &DstSubIdx) const { - SrcSubIdx = DstSubIdx = 0; // No sub-registers yet. - switch (MI.getOpcode()) { default: return false; @@ -164,6 +162,8 @@ SystemZInstrInfo::isMoveInstr(const MachineInstr& MI, "invalid register-register move instruction"); SrcReg = MI.getOperand(1).getReg(); DstReg = MI.getOperand(0).getReg(); + SrcSubIdx = MI.getOperand(1).getSubReg(); + DstSubIdx = MI.getOperand(0).getSubReg(); return true; } } |
