diff options
| author | Evan Cheng <evan.cheng@apple.com> | 2007-10-18 22:40:57 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2007-10-18 22:40:57 +0000 |
| commit | f0a0cddbcda344a90b7217b744c78dccec71851c (patch) | |
| tree | cfcdda0c59b826a9cc81f0b5b49ef5f0d401892f /lib/Target/Sparc | |
| parent | 58184e6878fdab651bc7c9a59dab2687ca82ede2 (diff) | |
- Added getOpcodeAfterMemoryUnfold(). It doesn't unfold an instruction, but only returns the opcode of the instruction post unfolding.
- Fix some copy+paste bugs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43153 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Sparc')
| -rw-r--r-- | lib/Target/Sparc/SparcRegisterInfo.cpp | 4 | ||||
| -rw-r--r-- | lib/Target/Sparc/SparcRegisterInfo.h | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/lib/Target/Sparc/SparcRegisterInfo.cpp b/lib/Target/Sparc/SparcRegisterInfo.cpp index 3055bf9dfe..2402de6542 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.cpp +++ b/lib/Target/Sparc/SparcRegisterInfo.cpp @@ -49,7 +49,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, } void SparcRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, - SmallVectorImpl<MachineOperand> Addr, + SmallVectorImpl<MachineOperand> &Addr, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const { unsigned Opc = 0; @@ -91,7 +91,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, } void SparcRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, - SmallVectorImpl<MachineOperand> Addr, + SmallVectorImpl<MachineOperand> &Addr, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const { unsigned Opc = 0; diff --git a/lib/Target/Sparc/SparcRegisterInfo.h b/lib/Target/Sparc/SparcRegisterInfo.h index 15a624f263..0139910072 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.h +++ b/lib/Target/Sparc/SparcRegisterInfo.h @@ -36,7 +36,7 @@ struct SparcRegisterInfo : public SparcGenRegisterInfo { const TargetRegisterClass *RC) const; void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, - SmallVectorImpl<MachineOperand> Addr, + SmallVectorImpl<MachineOperand> &Addr, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const; @@ -46,7 +46,7 @@ struct SparcRegisterInfo : public SparcGenRegisterInfo { const TargetRegisterClass *RC) const; void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, - SmallVectorImpl<MachineOperand> Addr, + SmallVectorImpl<MachineOperand> &Addr, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const; |