remove the V8 simple isel

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25534 91177308-0d34-0410-b5e6-96231b3b80d8

3 files changed, 4 insertions, 1840 deletions

diff --git a/lib/Target/Sparc/Sparc.h b/lib/Target/Sparc/Sparc.h
index 33bfdabd12..70f563bfa2 100644
--- a/lib/Target/Sparc/Sparc.h
+++ b/lib/Target/Sparc/Sparc.h
@@ -22,7 +22,6 @@ namespace llvm {
   class FunctionPass;
   class TargetMachine;
 
-  FunctionPass *createSparcV8SimpleInstructionSelector(TargetMachine &TM);
   FunctionPass *createSparcV8ISelDag(TargetMachine &TM);
 
   FunctionPass *createSparcV8CodePrinterPass(std::ostream &OS,
diff --git a/lib/Target/Sparc/SparcTargetMachine.cpp b/lib/Target/Sparc/SparcTargetMachine.cpp
index 08e38fc7a3..83cd308327 100644
--- a/lib/Target/Sparc/SparcTargetMachine.cpp
+++ b/lib/Target/Sparc/SparcTargetMachine.cpp
@@ -27,10 +27,6 @@ using namespace llvm;
 namespace {
   // Register the target.
   RegisterTarget<SparcV8TargetMachine> X("sparcv8","  SPARC V8 (experimental)");
-
-  cl::opt<bool> EnableV8DAGDAG("enable-v8-dag-isel", cl::Hidden,
-                                cl::desc("Enable DAG-to-DAG isel for V8"),
-                                cl::init(0));
 }
 
 /// SparcV8TargetMachine ctor - Create an ILP32 architecture model
@@ -83,18 +79,10 @@ bool SparcV8TargetMachine::addPassesToEmitFile(PassManager &PM,
   if (PrintMachineCode)
     PM.add(new PrintFunctionPass());
 
-  if (!EnableV8DAGDAG) {
-    // Replace malloc and free instructions with library calls.
-    PM.add(createLowerAllocationsPass());
-    PM.add(createLowerSelectPass());
-    // Make sure that no unreachable blocks are instruction selected.
-    PM.add(createUnreachableBlockEliminationPass());
-    PM.add(createSparcV8SimpleInstructionSelector(*this));
-  } else {
-    // Make sure that no unreachable blocks are instruction selected.
-    PM.add(createUnreachableBlockEliminationPass());
-    PM.add(createSparcV8ISelDag(*this));
-  }
+  // Make sure that no unreachable blocks are instruction selected.
+  PM.add(createUnreachableBlockEliminationPass());
+  
+  PM.add(createSparcV8ISelDag(*this));
 
   // Print machine instructions as they were initially generated.
   if (PrintMachineCode)
diff --git a/lib/Target/Sparc/SparcV8ISelSimple.cpp b/lib/Target/Sparc/SparcV8ISelSimple.cpp
deleted file mode 100644
index f10859d5b9..0000000000
--- a/lib/Target/Sparc/SparcV8ISelSimple.cpp
+++ /dev/null
@@ -1,1823 +0,0 @@
-//===-- InstSelectSimple.cpp - A simple instruction selector for SparcV8 --===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file defines a simple peephole instruction selector for the V8 target
-//
-//===----------------------------------------------------------------------===//
-
-#include "SparcV8.h"
-#include "SparcV8InstrInfo.h"
-#include "llvm/Support/Debug.h"
-#include "llvm/Instructions.h"
-#include "llvm/Pass.h"
-#include "llvm/Constants.h"
-#include "llvm/DerivedTypes.h"
-#include "llvm/CodeGen/IntrinsicLowering.h"
-#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/CodeGen/MachineFrameInfo.h"
-#include "llvm/CodeGen/MachineConstantPool.h"
-#include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/SSARegMap.h"
-#include "llvm/Target/TargetMachine.h"
-#include "llvm/Support/InstVisitor.h"
-#include "llvm/Support/CFG.h"
-#include <iostream>
-using namespace llvm;
-
-namespace {
-  struct V8ISel : public FunctionPass, public InstVisitor<V8ISel> {
-    TargetMachine &TM;
-    MachineFunction *F;                 // The function we are compiling into
-    MachineBasicBlock *BB;              // The current MBB we are compiling
-    int VarArgsOffset;                  // Offset from fp for start of varargs area
-
-    std::map<Value*, unsigned> RegMap;  // Mapping between Val's and SSA Regs
-
-    // MBBMap - Mapping between LLVM BB -> Machine BB
-    std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
-
-    V8ISel(TargetMachine &tm) : TM(tm), F(0), BB(0) {}
-
-    /// runOnFunction - Top level implementation of instruction selection for
-    /// the entire function.
-    ///
-    bool runOnFunction(Function &Fn);
-
-    virtual const char *getPassName() const {
-      return "SparcV8 Simple Instruction Selection";
-    }
-
-    /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
-    /// constant expression GEP support.
-    ///
-    void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
-                          Value *Src, User::op_iterator IdxBegin,
-                          User::op_iterator IdxEnd, unsigned TargetReg);
-
-    /// emitCastOperation - Common code shared between visitCastInst and
-    /// constant expression cast support.
-    ///
-    void emitCastOperation(MachineBasicBlock *BB,MachineBasicBlock::iterator IP,
-                           Value *Src, const Type *DestTy, unsigned TargetReg);
-
-    /// emitIntegerCast, emitFPToIntegerCast - Helper methods for
-    /// emitCastOperation.
-    ///
-    unsigned emitIntegerCast (MachineBasicBlock *BB,
-                              MachineBasicBlock::iterator IP,
-                              const Type *oldTy, unsigned SrcReg,
-                              const Type *newTy, unsigned DestReg,
-                              bool castToLong = false);
-    void emitFPToIntegerCast (MachineBasicBlock *BB,
-                              MachineBasicBlock::iterator IP, const Type *oldTy,
-                              unsigned SrcReg, const Type *newTy,
-                              unsigned DestReg);
-
-    /// visitBasicBlock - This method is called when we are visiting a new basic
-    /// block.  This simply creates a new MachineBasicBlock to emit code into
-    /// and adds it to the current MachineFunction.  Subsequent visit* for
-    /// instructions will be invoked for all instructions in the basic block.
-    ///
-    void visitBasicBlock(BasicBlock &LLVM_BB) {
-      BB = MBBMap[&LLVM_BB];
-    }
-
-    void emitOp64LibraryCall (MachineBasicBlock *MBB,
-                              MachineBasicBlock::iterator IP,
-                              unsigned DestReg, const char *FuncName,
-                              unsigned Op0Reg, unsigned Op1Reg);
-    void emitShift64 (MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
-                      Instruction &I, unsigned DestReg, unsigned Op0Reg,
-                      unsigned Op1Reg);
-    void visitBinaryOperator(Instruction &I);
-    void visitShiftInst (ShiftInst &SI) { visitBinaryOperator (SI); }
-    void visitSetCondInst(SetCondInst &I);
-    void visitCallInst(CallInst &I);
-    void visitReturnInst(ReturnInst &I);
-    void visitBranchInst(BranchInst &I);
-    void visitUnreachableInst(UnreachableInst &I) {}
-    void visitCastInst(CastInst &I);
-    void visitVAArgInst(VAArgInst &I);
-    void visitLoadInst(LoadInst &I);
-    void visitStoreInst(StoreInst &I);
-    void visitPHINode(PHINode &I) {}      // PHI nodes handled by second pass
-    void visitGetElementPtrInst(GetElementPtrInst &I);
-    void visitAllocaInst(AllocaInst &I);
-
-    void visitInstruction(Instruction &I) {
-      std::cerr << "Unhandled instruction: " << I;
-      abort();
-    }
-
-    /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
-    /// function, lowering any calls to unknown intrinsic functions into the
-    /// equivalent LLVM code.
-    void LowerUnknownIntrinsicFunctionCalls(Function &F);
-    void visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI);
-
-    void LoadArgumentsToVirtualRegs(Function *F);
-
-    /// SelectPHINodes - Insert machine code to generate phis.  This is tricky
-    /// because we have to generate our sources into the source basic blocks,
-    /// not the current one.
-    ///
-    void SelectPHINodes();
-
-    /// copyConstantToRegister - Output the instructions required to put the
-    /// specified constant into the specified register.
-    ///
-    void copyConstantToRegister(MachineBasicBlock *MBB,
-                                MachineBasicBlock::iterator IP,
-                                Constant *C, unsigned R);
-
-    /// makeAnotherReg - This method returns the next register number we haven't
-    /// yet used.
-    ///
-    /// Long values are handled somewhat specially.  They are always allocated
-    /// as pairs of 32 bit integer values.  The register number returned is the
-    /// lower 32 bits of the long value, and the regNum+1 is the upper 32 bits
-    /// of the long value.
-    ///
-    unsigned makeAnotherReg(const Type *Ty) {
-      assert(dynamic_cast<const SparcV8RegisterInfo*>(TM.getRegisterInfo()) &&
-             "Current target doesn't have SparcV8 reg info??");
-      const SparcV8RegisterInfo *MRI =
-        static_cast<const SparcV8RegisterInfo*>(TM.getRegisterInfo());
-      if (Ty == Type::LongTy || Ty == Type::ULongTy) {
-        const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
-        // Create the lower part
-        F->getSSARegMap()->createVirtualRegister(RC);
-        // Create the upper part.
-        return F->getSSARegMap()->createVirtualRegister(RC)-1;
-      }
-
-      // Add the mapping of regnumber => reg class to MachineFunction
-      const TargetRegisterClass *RC = MRI->getRegClassForType(Ty);
-      return F->getSSARegMap()->createVirtualRegister(RC);
-    }
-
-    unsigned getReg(Value &V) { return getReg (&V); } // allow refs.
-    unsigned getReg(Value *V) {
-      // Just append to the end of the current bb.
-      MachineBasicBlock::iterator It = BB->end();
-      return getReg(V, BB, It);
-    }
-    unsigned getReg(Value *V, MachineBasicBlock *MBB,
-                    MachineBasicBlock::iterator IPt) {
-      unsigned &Reg = RegMap[V];
-      if (Reg == 0) {
-        Reg = makeAnotherReg(V->getType());
-        RegMap[V] = Reg;
-      }
-      // If this operand is a constant, emit the code to copy the constant into
-      // the register here...
-      //
-      if (Constant *C = dyn_cast<Constant>(V)) {
-        copyConstantToRegister(MBB, IPt, C, Reg);
-        RegMap.erase(V);  // Assign a new name to this constant if ref'd again
-      } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
-        // Move the address of the global into the register
-        unsigned TmpReg = makeAnotherReg(V->getType());
-        BuildMI (*MBB, IPt, V8::SETHIi, 1, TmpReg).addGlobalAddress (GV);
-        BuildMI (*MBB, IPt, V8::ORri, 2, Reg).addReg (TmpReg)
-          .addGlobalAddress (GV);
-        RegMap.erase(V);  // Assign a new name to this address if ref'd again
-      }
-
-      return Reg;
-    }
-
-  };
-}
-
-FunctionPass *llvm::createSparcV8SimpleInstructionSelector(TargetMachine &TM) {
-  return new V8ISel(TM);
-}
-
-enum TypeClass {
-  cByte, cShort, cInt, cLong, cFloat, cDouble
-};
-
-static TypeClass getClass (const Type *T) {
-  switch (T->getTypeID()) {
-    case Type::UByteTyID:  case Type::SByteTyID:  return cByte;
-    case Type::UShortTyID: case Type::ShortTyID:  return cShort;
-    case Type::PointerTyID:
-    case Type::UIntTyID:   case Type::IntTyID:    return cInt;
-    case Type::ULongTyID:  case Type::LongTyID:   return cLong;
-    case Type::FloatTyID:                         return cFloat;
-    case Type::DoubleTyID:                        return cDouble;
-    default:
-      assert (0 && "Type of unknown class passed to getClass?");
-      return cByte;
-  }
-}
-
-static TypeClass getClassB(const Type *T) {
-  if (T == Type::BoolTy) return cByte;
-  return getClass(T);
-}
-
-/// copyConstantToRegister - Output the instructions required to put the
-/// specified constant into the specified register.
-///
-void V8ISel::copyConstantToRegister(MachineBasicBlock *MBB,
-                                    MachineBasicBlock::iterator IP,
-                                    Constant *C, unsigned R) {
-  if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
-    switch (CE->getOpcode()) {
-    case Instruction::GetElementPtr:
-      emitGEPOperation(MBB, IP, CE->getOperand(0),
-                       CE->op_begin()+1, CE->op_end(), R);
-      return;
-    case Instruction::Cast:
-      emitCastOperation(MBB, IP, CE->getOperand(0), CE->getType(), R);
-      return;
-    default:
-      std::cerr << "Copying this constant expr not yet handled: " << *CE;
-      abort();
-    }
-  } else if (isa<UndefValue>(C)) {
-    BuildMI(*MBB, IP, V8::IMPLICIT_DEF_Int, 0, R);
-    if (getClassB (C->getType ()) == cLong)
-      BuildMI(*MBB, IP, V8::IMPLICIT_DEF_Int, 0, R+1);
-    return;
-  }
-
-  if (C->getType()->isIntegral ()) {
-    unsigned Class = getClassB (C->getType ());
-    if (Class == cLong) {
-      unsigned TmpReg = makeAnotherReg (Type::IntTy);
-      unsigned TmpReg2 = makeAnotherReg (Type::IntTy);
-      // Copy the value into the register pair.
-      // R = top(more-significant) half, R+1 = bottom(less-significant) half
-      uint64_t Val = cast<ConstantInt>(C)->getRawValue();
-      copyConstantToRegister(MBB, IP, ConstantUInt::get(Type::UIntTy,
-                             Val >> 32), R);
-      copyConstantToRegister(MBB, IP, ConstantUInt::get(Type::UIntTy,
-                             Val & 0xffffffffU), R+1);
-      return;
-    }
-
-    assert(Class <= cInt && "Type not handled yet!");
-    unsigned Val;
-
-    if (C->getType() == Type::BoolTy) {
-      Val = (C == ConstantBool::True);
-    } else {
-      ConstantIntegral *CI = cast<ConstantIntegral> (C);
-      Val = CI->getRawValue();
-    }
-    if (C->getType()->isSigned()) {
-      switch (Class) {
-        case cByte:  Val =  (int8_t) Val; break;
-        case cShort: Val = (int16_t) Val; break;
-        case cInt:   Val = (int32_t) Val; break;
-      }
-    } else {
-      switch (Class) {
-        case cByte:  Val =  (uint8_t) Val; break;
-        case cShort: Val = (uint16_t) Val; break;
-        case cInt:   Val = (uint32_t) Val; break;
-      }
-    }
-    if (Val == 0) {
-      BuildMI (*MBB, IP, V8::ORrr, 2, R).addReg (V8::G0).addReg(V8::G0);
-    } else if ((int)Val >= -4096 && (int)Val <= 4095) {
-      BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addSImm(Val);
-    } else {
-      unsigned TmpReg = makeAnotherReg (C->getType ());
-      BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg)
-        .addSImm (((uint32_t) Val) >> 10);
-      BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg)
-        .addSImm (((uint32_t) Val) & 0x03ff);
-      return;
-    }
-  } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
-    // We need to spill the constant to memory...
-    MachineConstantPool *CP = F->getConstantPool();
-    unsigned CPI = CP->getConstantPoolIndex(CFP);
-    const Type *Ty = CFP->getType();
-    unsigned TmpReg = makeAnotherReg (Type::UIntTy);
-    unsigned AddrReg = makeAnotherReg (Type::UIntTy);
-
-    assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
-    unsigned LoadOpcode = Ty == Type::FloatTy ? V8::LDFri : V8::LDDFri;
-    BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addConstantPoolIndex (CPI);
-    BuildMI (*MBB, IP, V8::ORri, 2, AddrReg).addReg (TmpReg)
-      .addConstantPoolIndex (CPI);
-    BuildMI (*MBB, IP, LoadOpcode, 2, R).addReg (AddrReg).addSImm (0);
-  } else if (isa<ConstantPointerNull>(C)) {
-    // Copy zero (null pointer) to the register.
-    BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addSImm (0);
-  } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
-    // Copy it with a SETHI/OR pair; the JIT + asmwriter should recognize
-    // that SETHI %reg,global == SETHI %reg,%hi(global) and
-    // OR %reg,global,%reg == OR %reg,%lo(global),%reg.
-    unsigned TmpReg = makeAnotherReg (C->getType ());
-    BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addGlobalAddress(GV);
-    BuildMI (*MBB, IP, V8::ORri, 2, R).addReg(TmpReg).addGlobalAddress(GV);
-  } else {
-    std::cerr << "Offending constant: " << *C << "\n";
-    assert (0 && "Can't copy this kind of constant into register yet");
-  }
-}
-
-void V8ISel::LoadArgumentsToVirtualRegs (Function *LF) {
-  static const unsigned IncomingArgRegs[] = { V8::I0, V8::I1, V8::I2,
-    V8::I3, V8::I4, V8::I5 };
-
-  // Add IMPLICIT_DEFs of input regs.
-  unsigned ArgNo = 0;
-  for (Function::arg_iterator I = LF->arg_begin(), E = LF->arg_end();
-       I != E && ArgNo < 6; ++I, ++ArgNo) {
-    switch (getClassB(I->getType())) {
-    case cByte:
-    case cShort:
-    case cInt:
-    case cFloat:
-      BuildMI(BB, V8::IMPLICIT_DEF_Int, 0, IncomingArgRegs[ArgNo]);
-      break;
-    case cDouble:
-    case cLong:
-      // Double and Long use register pairs.
-      BuildMI(BB, V8::IMPLICIT_DEF_Int, 0, IncomingArgRegs[ArgNo]);
-      ++ArgNo;
-      if (ArgNo < 6)
-        BuildMI(BB, V8::IMPLICIT_DEF_Int, 0, IncomingArgRegs[ArgNo]);
-      break;
-    default:
-      assert (0 && "type not handled");
-      return;
-    }
-  }
-
-  const unsigned *IAREnd = &IncomingArgRegs[6];
-  const unsigned *IAR = &IncomingArgRegs[0];
-  unsigned ArgOffset = 68;
-
-  // Store registers onto stack if this is a varargs function.
-  // FIXME: This doesn't really pertain to "loading arguments into
-  // virtual registers", so it's not clear that it really belongs here.
-  // FIXME: We could avoid storing any args onto the stack that don't
-  // need to be in memory, because they come before the ellipsis in the
-  // parameter list (and thus could never be accessed through va_arg).
-  if (LF->getFunctionType()->isVarArg()) {
-    for (unsigned i = 0; i < 6; ++i) {
-      int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
-      assert (IAR != IAREnd
-              && "About to dereference past end of IncomingArgRegs");
-      BuildMI (BB, V8::STri, 3).addFrameIndex (FI).addSImm (0).addReg (*IAR++);
-      ArgOffset += 4;
-    }
-    // Reset the pointers now that we're done.
-    ArgOffset = 68;
-    IAR = &IncomingArgRegs[0];
-  }
-
-  // Copy args out of their incoming hard regs or stack slots into virtual regs.
-  for (Function::arg_iterator I = LF->arg_begin(), E = LF->arg_end(); I != E; ++I) {
-    Argument &A = *I;
-    unsigned ArgReg = getReg (A);
-    if (getClassB (A.getType ()) < cLong) {
-      // Get it out of the incoming arg register
-      if (ArgOffset < 92) {
-        assert (IAR != IAREnd
-                && "About to dereference past end of IncomingArgRegs");
-        BuildMI (BB, V8::ORrr, 2, ArgReg).addReg (V8::G0).addReg (*IAR++);
-      } else {
-        int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
-        BuildMI (BB, V8::LDri, 3, ArgReg).addFrameIndex (FI).addSImm (0);
-      }
-      ArgOffset += 4;
-    } else if (getClassB (A.getType ()) == cFloat) {
-      if (ArgOffset < 92) {
-        // Single-fp args are passed in integer registers; go through
-        // memory to get them out of integer registers and back into fp. (Bleh!)
-        unsigned FltAlign = TM.getTargetData().getFloatAlignment();
-        int FI = F->getFrameInfo()->CreateStackObject(4, FltAlign);
-        assert (IAR != IAREnd
-                && "About to dereference past end of IncomingArgRegs");
-        BuildMI (BB, V8::STri, 3).addFrameIndex (FI).addSImm (0).addReg (*IAR++);
-        BuildMI (BB, V8::LDFri, 2, ArgReg).addFrameIndex (FI).addSImm (0);
-      } else {
-        int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
-        BuildMI (BB, V8::LDFri, 3, ArgReg).addFrameIndex (FI).addSImm (0);
-      }
-      ArgOffset += 4;
-    } else if (getClassB (A.getType ()) == cDouble) {
-      // Double-fp args are passed in pairs of integer registers; go through
-      // memory to get them out of integer registers and back into fp. (Bleh!)
-      // We'd like to 'ldd' these right out of the incoming-args area,
-      // but it might not be 8-byte aligned (e.g., call x(int x, double d)).
-      unsigned DblAlign = TM.getTargetData().getDoubleAlignment();
-      int FI = F->getFrameInfo()->CreateStackObject(8, DblAlign);
-      if (ArgOffset < 92 && IAR != IAREnd) {
-        BuildMI (BB, V8::STri, 3).addFrameIndex (FI).addSImm (0).addReg (*IAR++);
-      } else {
-        unsigned TempReg = makeAnotherReg (Type::IntTy);
-        BuildMI (BB, V8::LDri, 2, TempReg).addFrameIndex (FI).addSImm (0);
-        BuildMI (BB, V8::STri, 3).addFrameIndex (FI).addSImm (0).addReg (TempReg);
-      }
-      ArgOffset += 4;
-      if (ArgOffset < 92 && IAR != IAREnd) {
-        BuildMI (BB, V8::STri, 3).addFrameIndex (FI).addSImm (4).addReg (*IAR++);
-      } else {
-        unsigned TempReg = makeAnotherReg (Type::IntTy);
-        BuildMI (BB, V8::LDri, 2, TempReg).addFrameIndex (FI).addSImm (4);
-        BuildMI (BB, V8::STri, 3).addFrameIndex (FI).addSImm (4).addReg (TempReg);
-      }
-      ArgOffset += 4;
-      BuildMI (BB, V8::LDDFri, 2, ArgReg).addFrameIndex (FI).addSImm (0);
-    } else if (getClassB (A.getType ()) == cLong) {
-      // do the first half...
-      if (ArgOffset < 92) {
-        assert (IAR != IAREnd
-                && "About to dereference past end of IncomingArgRegs");
-        BuildMI (BB, V8::ORrr, 2, ArgReg).addReg (V8::G0).addReg (*IAR++);
-      } else {
-        int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
-        BuildMI (BB, V8::LDri, 2, ArgReg).addFrameIndex (FI).addSImm (0);
-      }
-      ArgOffset += 4;
-      // ...then do the second half
-      if (ArgOffset < 92) {
-        assert (IAR != IAREnd
-                && "About to dereference past end of IncomingArgRegs");
-        BuildMI (BB, V8::ORrr, 2, ArgReg+1).addReg (V8::G0).addReg (*IAR++);
-      } else {
-        int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
-        BuildMI (BB, V8::LDri, 2, ArgReg+1).addFrameIndex (FI).addSImm (0);
-      }
-      ArgOffset += 4;
-    } else {
-      assert (0 && "Unknown class?!");
-    }
-  }
-
-  // If the function takes variable number of arguments, remember the fp
-  // offset for the start of the first vararg value... this is used to expand
-  // llvm.va_start.
-  if (LF->getFunctionType ()->isVarArg ())
-    VarArgsOffset = ArgOffset;
-}
-
-void V8ISel::SelectPHINodes() {
-  const TargetInstrInfo &TII = *TM.getInstrInfo();
-  const Function &LF = *F->getFunction();  // The LLVM function...
-  for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
-    const BasicBlock *BB = I;
-    MachineBasicBlock &MBB = *MBBMap[I];
-
-    // Loop over all of the PHI nodes in the LLVM basic block...
-    MachineBasicBlock::iterator PHIInsertPoint = MBB.begin();
-    for (BasicBlock::const_iterator I = BB->begin();
-         PHINode *PN = const_cast<PHINode*>(dyn_cast<PHINode>(I)); ++I) {
-
-      // Create a new machine instr PHI node, and insert it.
-      unsigned PHIReg = getReg(*PN);
-      MachineInstr *PhiMI = BuildMI(MBB, PHIInsertPoint,
-                                    V8::PHI, PN->getNumOperands(), PHIReg);
-
-      MachineInstr *LongPhiMI = 0;
-      if (PN->getType() == Type::LongTy || PN->getType() == Type::ULongTy)
-        LongPhiMI = BuildMI(MBB, PHIInsertPoint,
-                            V8::PHI, PN->getNumOperands(), PHIReg+1);
-
-      // PHIValues - Map of blocks to incoming virtual registers.  We use this
-      // so that we only initialize one incoming value for a particular block,
-      // even if the block has multiple entries in the PHI node.
-      //
-      std::map<MachineBasicBlock*, unsigned> PHIValues;
-
-      for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
-        MachineBasicBlock *PredMBB = 0;
-        for (MachineBasicBlock::pred_iterator PI = MBB.pred_begin (),
-             PE = MBB.pred_end (); PI != PE; ++PI)
-          if (PN->getIncomingBlock(i) == (*PI)->getBasicBlock()) {
-            PredMBB = *PI;
-            break;
-          }
-        assert (PredMBB && "Couldn't find incoming machine-cfg edge for phi");
-
-        unsigned ValReg;
-        std::map<MachineBasicBlock*, unsigned>::iterator EntryIt =
-          PHIValues.lower_bound(PredMBB);
-
-        if (EntryIt != PHIValues.end() && EntryIt->first == PredMBB) {
-          // We already inserted an initialization of the register for this
-          // predecessor.  Recycle it.
-          ValReg = EntryIt->second;
-
-        } else {
-          // Get the incoming value into a virtual register.
-          //
-          Value *Val = PN->getIncomingValue(i);
-
-          // If this is a constant or GlobalValue, we may have to insert code
-          // into the basic block to compute it into a virtual register.
-          if ((isa<Constant>(Val) && !isa<ConstantExpr>(Val)) ||
-              isa<GlobalValue>(Val)) {
-            // Simple constants get emitted at the end of the basic block,
-            // before any terminator instructions.  We "know" that the code to
-            // move a constant into a register will never clobber any flags.
-            ValReg = getReg(Val, PredMBB, PredMBB->getFirstTerminator());
-          } else {
-            // Because we don't want to clobber any values which might be in
-            // physical registers with the computation of this constant (which
-            // might be arbitrarily complex if it is a constant expression),
-            // just insert the computation at the top of the basic block.
-            MachineBasicBlock::iterator PI = PredMBB->begin();
-
-            // Skip over any PHI nodes though!
-            while (PI != PredMBB->end() && PI->getOpcode() == V8::PHI)
-              ++PI;
-
-            ValReg = getReg(Val, PredMBB, PI);
-          }
-
-          // Remember that we inserted a value for this PHI for this predecessor
-          PHIValues.insert(EntryIt, std::make_pair(PredMBB, ValReg));
-        }
-
-        PhiMI->addRegOperand(ValReg);
-        PhiMI->addMachineBasicBlockOperand(PredMBB);
-        if (LongPhiMI) {
-          LongPhiMI->addRegOperand(ValReg+1);
-          LongPhiMI->addMachineBasicBlockOperand(PredMBB);
-        }
-      }
-
-      // Now that we emitted all of the incoming values for the PHI node, make
-      // sure to reposition the InsertPoint after the PHI that we just added.
-      // This is needed because we might have inserted a constant into this
-      // block, right after the PHI's which is before the old insert point!
-      PHIInsertPoint = LongPhiMI ? LongPhiMI : PhiMI;
-      ++PHIInsertPoint;
-    }
-  }
-}
-
-bool V8ISel::runOnFunction(Function &Fn) {
-  // First pass over the function, lower any unknown intrinsic functions
-  // with the IntrinsicLowering class.
-  LowerUnknownIntrinsicFunctionCalls(Fn);
-
-  F = &MachineFunction::construct(&Fn, TM);
-
-  // Create all of the machine basic blocks for the function...
-  for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
-    F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
-
-  BB = &F->front();
-
-  // Set up a frame object for the return address.  This is used by the
-  // llvm.returnaddress & llvm.frameaddress intrinisics.
-  //ReturnAddressIndex = F->getFrameInfo()->CreateFixedObject(4, -4);
-
-  // Copy incoming arguments off of the stack and out of fixed registers.
-  LoadArgumentsToVirtualRegs(&Fn);
-
-  // Instruction select everything except PHI nodes
-  visit(Fn);
-
-  // Select the PHI nodes
-  SelectPHINodes();
-
-  RegMap.clear();
-  MBBMap.clear();
-  F = 0;
-  // We always build a machine code representation for the function
-  return true;
-}
-
-void V8ISel::visitCastInst(CastInst &I) {
-  Value *Op = I.getOperand(0);
-  unsigned DestReg = getReg(I);
-  MachineBasicBlock::iterator MI = BB->end();
-  emitCastOperation(BB, MI, Op, I.getType(), DestReg);
-}
-
-unsigned V8ISel::emitIntegerCast (MachineBasicBlock *BB,
-                              MachineBasicBlock::iterator IP, const Type *oldTy,
-                              unsigned SrcReg, const Type *newTy,
-                              unsigned DestReg, bool castToLong) {
-  unsigned shiftWidth = 32 - (8 * TM.getTargetData ().getTypeSize (newTy));
-  if (oldTy == newTy || (!castToLong && shiftWidth == 0)) {
-    // No-op cast - just emit a copy; assume the reg. allocator will zap it.
-    BuildMI (*BB, IP, V8::ORrr, 2, DestReg).addReg (V8::G0).addReg(SrcReg);
-    return SrcReg;
-  }
-  // Emit left-shift, then right-shift to sign- or zero-extend.
-  unsigned TmpReg = makeAnotherReg (newTy);
-  BuildMI (*BB, IP, V8::SLLri, 2, TmpReg).addZImm (shiftWidth).addReg(SrcReg);
-  if (newTy->isSigned ()) { // sign-extend with SRA
-    BuildMI(*BB, IP, V8::SRAri, 2, DestReg).addZImm (shiftWidth).addReg(TmpReg);
-  } else { // zero-extend with SRL
-    BuildMI(*BB, IP, V8::SRLri, 2, DestReg).addZImm (shiftWidth).addReg(TmpReg);
-  }
-  // Return the temp reg. in case this is one half of a cast to long.
-  return TmpReg;
-}
-
-void V8ISel::emitFPToIntegerCast (MachineBasicBlock *BB,
-                                  MachineBasicBlock::iterator IP,
-                                  const Type *oldTy, unsigned SrcReg,
-                                  const Type *newTy, unsigned DestReg) {
-  unsigned FPCastOpcode, FPStoreOpcode, FPSize, FPAlign;
-  unsigned oldTyClass = getClassB(oldTy);
-  if (oldTyClass == cFloat) {
-    FPCastOpcode = V8::FSTOI; FPStoreOpcode = V8::STFri; FPSize = 4;
-    FPAlign = TM.getTargetData().getFloatAlignment();
-  } else { // it's a double
-    FPCastOpcode = V8::FDTOI; FPStoreOpcode = V8::STDFri; FPSize = 8;
-    FPAlign = TM.getTargetData().getDoubleAlignment();
-  }
-  unsigned TempReg = makeAnotherReg (oldTy);
-  BuildMI (*BB, IP, FPCastOpcode, 1, TempReg).addReg (SrcReg);
-  int FI = F->getFrameInfo()->CreateStackObject(FPSize, FPAlign);
-  BuildMI (*BB, IP, FPStoreOpcode, 3).addFrameIndex (FI).addSImm (0)
-    .addReg (TempReg);
-  unsigned TempReg2 = makeAnotherReg (newTy);
-  BuildMI (*BB, IP, V8::LDri, 3, TempReg2).addFrameIndex (FI).addSImm (0);
-  emitIntegerCast (BB, IP, Type::IntTy, TempReg2, newTy, DestReg);
-}
-
-/// emitCastOperation - Common code shared between visitCastInst and constant
-/// expression cast support.
-///
-void V8ISel::emitCastOperation(MachineBasicBlock *BB,
-                               MachineBasicBlock::iterator IP, Value *Src,
-                               const Type *DestTy, unsigned DestReg) {
-  const Type *SrcTy = Src->getType();
-  unsigned SrcClass = getClassB(SrcTy);
-  unsigned DestClass = getClassB(DestTy);
-  unsigned SrcReg = getReg(Src, BB, IP);
-
-  const Type *oldTy = SrcTy;
-  const Type *newTy = DestTy;
-  unsigned oldTyClass = SrcClass;
-  unsigned newTyClass = DestClass;
-
-  if (oldTyClass < cLong && newTyClass < cLong) {
-    emitIntegerCast (BB, IP, oldTy, SrcReg, newTy, DestReg);
-  } else switch (newTyClass) {
-    case cByte:
-    case cShort:
-    case cInt:
-      switch (oldTyClass) {
-      case cLong:
-        // Treat it like a cast from the lower half of the value.
-        emitIntegerCast (BB, IP, Type::IntTy, SrcReg+1, newTy, DestReg);
-        break;
-      case cFloat:
-      case cDouble:
-        emitFPToIntegerCast (BB, IP, oldTy, SrcReg, newTy, DestReg);
-        break;
-      default: goto not_yet;
-      }
-      return;
-
-    case cFloat:
-      switch (oldTyClass) {
-      case cLong: goto not_yet;
-      case cFloat:
-        BuildMI (*BB, IP, V8::FMOVS, 1, DestReg).addReg (SrcReg);
-        break;
-      case cDouble:
-        BuildMI (*BB, IP, V8::FDTOS, 1, DestReg).addReg (SrcReg);
-        break;
-      default: {
-        unsigned FltAlign = TM.getTargetData().getFloatAlignment();
-        // cast integer type to float.  Store it to a stack slot and then load
-        // it using ldf into a floating point register. then do fitos.
-        unsigned TmpReg = makeAnotherReg (newTy);
-        int FI = F->getFrameInfo()->CreateStackObject(4, FltAlign);
-        BuildMI (*BB, IP, V8::STri, 3).addFrameIndex (FI).addSImm (0)
-          .addReg (SrcReg);
-        BuildMI (*BB, IP, V8::LDFri, 2, TmpReg).addFrameIndex (FI).addSImm (0);
-        BuildMI (*BB, IP, V8::FITOS, 1, DestReg).addReg(TmpReg);
-        break;
-      }
-      }
-      return;
-
-    case cDouble:
-      switch (oldTyClass) {
-      case cLong: goto not_yet;
-      case cFloat:
-        BuildMI (*BB, IP, V8::FSTOD, 1, DestReg).addReg (SrcReg);
-        break;
-      case cDouble: // use double move pseudo-instr
-        BuildMI (*BB, IP, V8::FpMOVD, 1, DestReg).addReg (SrcReg);
-        break;
-      default: {
-        unsigned DoubleAlignment = TM.getTargetData().getDoubleAlignment();
-        unsigned TmpReg = makeAnotherReg (newTy);
-        int FI = F->getFrameInfo()->CreateStackObject(8, DoubleAlignment);
-        BuildMI (*BB, IP, V8::STri, 3).addFrameIndex (FI).addSImm (0)
-          .addReg (SrcReg);
-        BuildMI (*BB, IP, V8::LDDFri, 2, TmpReg).addFrameIndex (FI).addSImm (0);
-        BuildMI (*BB, IP, V8::FITOD, 1, DestReg).addReg(TmpReg);
-        break;
-      }
-      }
-      return;
-
-    case cLong:
-      switch (oldTyClass) {
-      case cByte:
-      case cShort:
-      case cInt: {
-        // Cast to (u)int in the bottom half, and sign(zero) extend in the top
-        // half.
-        const Type *OldHalfTy = oldTy->isSigned() ? Type::IntTy : Type::UIntTy;
-        const Type *NewHalfTy = newTy->isSigned() ? Type::IntTy : Type::UIntTy;
-        unsigned TempReg = emitIntegerCast (BB, IP, OldHalfTy, SrcReg,
-                                            NewHalfTy, DestReg+1, true);
-        if (newTy->isSigned ()) {
-          BuildMI (*BB, IP, V8::SRAri, 2, DestReg).addReg (TempReg)
-            .addZImm (31);
-        } else {
-          BuildMI (*BB, IP, V8::ORrr, 2, DestReg).addReg (V8::G0)
-            .addReg (V8::G0);
-        }
-        break;
-      }
-      case cLong:
-        // Just copy both halves.
-        BuildMI (*BB, IP, V8::ORrr, 2, DestReg).addReg (V8::G0).addReg (SrcReg);
-        BuildMI (*BB, IP, V8::ORrr, 2, DestReg+1).addReg (V8::G0)
-          .addReg (SrcReg+1);
-        break;
-      default: goto not_yet;
-      }
-      return;
-
-    default: goto not_yet;
-  }
-  return;
-not_yet:
-  std::cerr << "Sorry, cast still unsupported: SrcTy = " << *SrcTy
-            << ", DestTy = " << *DestTy << "\n";
-  abort ();
-}
-
-void V8ISel::visitLoadInst(LoadInst &I) {
-  unsigned DestReg = getReg (I);
-  unsigned PtrReg = getReg (I.getOperand (0));
-  switch (getClassB (I.getType ())) {
-   case cByte:
-    if (I.getType ()->isSigned ())
-      BuildMI (BB, V8::LDSBri, 2, DestReg).addReg (PtrReg).addSImm(0);
-    else
-      BuildMI (BB, V8::LDUBri, 2, DestReg).addReg (PtrReg).addSImm(0);
-    return;
-   case cShort:
-    if (I.getType ()->isSigned ())
-      BuildMI (BB, V8::LDSHri, 2, DestReg).addReg (PtrReg).addSImm(0);
-    else
-      BuildMI (BB, V8::LDUHri, 2, DestReg).addReg (PtrReg).addSImm(0);
-    return;
-   case cInt:
-    BuildMI (BB, V8::LDri, 2, DestReg).addReg (PtrReg).addSImm(0);
-    return;
-   case cLong:
-    BuildMI (BB, V8::LDri, 2, DestReg).addReg (PtrReg).addSImm(0);
-    BuildMI (BB, V8::LDri, 2, DestReg+1).addReg (PtrReg).addSImm(4);
-    return;
-   case cFloat:
-    BuildMI (BB, V8::LDFri, 2, DestReg).addReg (PtrReg).addSImm(0);
-    return;
-   case cDouble:
-    BuildMI (BB, V8::LDDFri, 2, DestReg).addReg (PtrReg).addSImm(0);
-    return;
-   default:
-    std::cerr << "Load instruction not handled: " << I;
-    abort ();
-    return;
-  }
-}
-
-void V8ISel::visitStoreInst(StoreInst &I) {
-  Value *SrcVal = I.getOperand (0);
-  unsigned SrcReg = getReg (SrcVal);
-  unsigned PtrReg = getReg (I.getOperand (1));
-  switch (getClassB (SrcVal->getType ())) {
-   case cByte:
-    BuildMI (BB, V8::STBri, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
-    return;
-   case cShort:
-    BuildMI (BB, V8::STHri, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
-    return;
-   case cInt:
-    BuildMI (BB, V8::STri, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
-    return;
-   case cLong:
-    BuildMI (BB, V8::STri, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
-    BuildMI (BB, V8::STri, 3).addReg (PtrReg).addSImm (4).addReg (SrcReg+1);
-    return;
-