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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-05-26 01:21:14 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2010-05-26 01:21:14 +0000 |
| commit | b555609e73f5091bf8180c0875fb1fa6c5ad0e7a (patch) | |
| tree | 96d997b82dbd5e9fa80e40dd406b0e55db187b2d /lib/Target/Sparc | |
| parent | a4e4ffd389497eb28f5fe91521fb71da4340e5d6 (diff) | |
Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism."
This reverts commit 104654.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104660 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Sparc')
| -rw-r--r-- | lib/Target/Sparc/SparcRegisterInfo.td | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/lib/Target/Sparc/SparcRegisterInfo.td b/lib/Target/Sparc/SparcRegisterInfo.td index fede9299cc..2b05c19bf1 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.td +++ b/lib/Target/Sparc/SparcRegisterInfo.td @@ -20,11 +20,6 @@ class SparcCtrlReg<string n>: Register<n> { let Namespace = "SP"; } -let Namespace = "SP" in { -def sub_even : SubRegIndex; -def sub_odd : SubRegIndex; -} - // Registers are identified with 5-bit ID numbers. // Ri - 32-bit integer registers class Ri<bits<5> num, string n> : SparcReg<n> { @@ -38,7 +33,6 @@ class Rf<bits<5> num, string n> : SparcReg<n> { class Rd<bits<5> num, string n, list<Register> subregs> : SparcReg<n> { let Num = num; let SubRegs = subregs; - let SubRegIndices = [sub_even, sub_odd]; } // Control Registers |