diff options
| author | Chris Lattner <sabre@nondot.org> | 2006-01-15 19:15:46 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2006-01-15 19:15:46 +0000 |
| commit | 7f9975a793c575c3e4081e2b0dc3c950681cd316 (patch) | |
| tree | 4d2ccf3012d0de36f1c3a0c25ae73a5b54780f08 /lib/Target/Sparc | |
| parent | bf40c4bfe1607980ea570ac69bf134cc4e58d0ca (diff) | |
Disable a broken optimization
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25340 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Sparc')
| -rw-r--r-- | lib/Target/Sparc/SparcISelDAGToDAG.cpp | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp index 96b442cfb6..56dc26a2fa 100644 --- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp +++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp @@ -445,7 +445,8 @@ SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, ObjSize = 8; // If we can store this directly into the outgoing slot, do so. We can // do this when all ArgRegs are used and if the outgoing slot is aligned. - if (RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) { + // FIXME: McGill/misr fails with this. + if (0 && RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) { ValToStore = Val; break; } |