diff options
| author | Chris Lattner <sabre@nondot.org> | 2005-12-19 07:57:53 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2005-12-19 07:57:53 +0000 |
| commit | 7c423b4df11d64593c450df9f645a27e509aae14 (patch) | |
| tree | 3fcd51b3ae6cd6846fae95c595178e3ebfc2e015 /lib/Target/Sparc | |
| parent | 1b80f4d2c6e02e0784a7fee89df6d840ec4e690e (diff) | |
Fix pifft by correcting the case when a i64/f64 straddles O5 and memory:
we were storing into [FP+88] instead of [FP+92].
Improve codegen by emitting [FP+92], instead of emitting a copy of FP into
another GPR which wouldn't be coallesced because FP isn't register allocated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24859 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Sparc')
| -rw-r--r-- | lib/Target/Sparc/SparcISelDAGToDAG.cpp | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp index 195a32e7fb..6c84d28311 100644 --- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp +++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp @@ -456,6 +456,8 @@ SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, if (RegValuesToPass.size() >= 6) { ValToStore = Lo; + ArgOffset += 4; + ObjSize = 4; } else { RegValuesToPass.push_back(Lo); } @@ -464,7 +466,7 @@ SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, if (ValToStore.Val) { if (!StackPtr.Val) { - StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(), V8::O6, MVT::i32); + StackPtr = DAG.getRegister(V8::O6, MVT::i32); NullSV = DAG.getSrcValue(NULL); } SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); @@ -893,6 +895,7 @@ SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) { switch (N->getOpcode()) { default: break; + case ISD::Register: return Op; case ISD::FrameIndex: { int FI = cast<FrameIndexSDNode>(N)->getIndex(); if (N->hasOneUse()) |