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| author | Chris Lattner <sabre@nondot.org> | 2006-01-31 07:43:33 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2006-01-31 07:43:33 +0000 |
| commit | 76e7a441cf04798eb183a375870c45bcaeacd9ae (patch) | |
| tree | dbeb9732460d4f5ec27ba2a4ea1bd8adb6c4fb35 /lib/Target/Sparc | |
| parent | a45b4925e19e6f70b37b27280e41cafd8a0095a3 (diff) | |
More notes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25845 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Sparc')
| -rw-r--r-- | lib/Target/Sparc/README.txt | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/lib/Target/Sparc/README.txt b/lib/Target/Sparc/README.txt index 5ec8da8029..e3bc2c63d7 100644 --- a/lib/Target/Sparc/README.txt +++ b/lib/Target/Sparc/README.txt @@ -37,4 +37,18 @@ t1: 1) should be replaced with a brz in V9 mode. -* Same as above, but emit conditional move on register zero (p192) in V9 mode. +* Same as above, but emit conditional move on register zero (p192) in V9 + mode. Testcase: + +int %t1(int %a, int %b) { + %C = seteq int %a, 0 + %D = select bool %C, int %a, int %b + ret int %D +} + +* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling + with the Y register, if they are faster. + +* Codegen bswap(load)/store(bswap) -> load/store ASI + + |