kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC

and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26255 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 18 insertions, 41 deletions

diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
index d80c0064f3..e66e713cda 100644
--- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp
+++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
@@ -1075,41 +1075,6 @@ void SparcDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
   
   switch (N->getOpcode()) {
   default: break;
-  case ISD::ADD_PARTS: {
-    SDOperand LHSL, LHSH, RHSL, RHSH;
-    Select(LHSL, N->getOperand(0));
-    Select(LHSH, N->getOperand(1));
-    Select(RHSL, N->getOperand(2));
-    Select(RHSH, N->getOperand(3));
-    // FIXME, handle immediate RHS.
-    SDOperand Low =
-      SDOperand(CurDAG->getTargetNode(SP::ADDCCrr, MVT::i32, MVT::Flag,
-                                      LHSL, RHSL), 0);
-    SDOperand Hi =
-      SDOperand(CurDAG->getTargetNode(SP::ADDXrr, MVT::i32, LHSH, RHSH, 
-                                      Low.getValue(1)), 0);
-    CodeGenMap[SDOperand(N, 0)] = Low;
-    CodeGenMap[SDOperand(N, 1)] = Hi;
-    Result = Op.ResNo ? Hi : Low;
-    return;
-  }
-  case ISD::SUB_PARTS: {
-    SDOperand LHSL, LHSH, RHSL, RHSH;
-    Select(LHSL, N->getOperand(0));
-    Select(LHSH, N->getOperand(1));
-    Select(RHSL, N->getOperand(2));
-    Select(RHSH, N->getOperand(3));
-    SDOperand Low =
-      SDOperand(CurDAG->getTargetNode(SP::SUBCCrr, MVT::i32, MVT::Flag,
-                                      LHSL, RHSL), 0);
-    SDOperand Hi =
-      SDOperand(CurDAG->getTargetNode(SP::SUBXrr, MVT::i32, LHSH, RHSH, 
-                                      Low.getValue(1)), 0);
-    CodeGenMap[SDOperand(N, 0)] = Low;
-    CodeGenMap[SDOperand(N, 1)] = Hi;
-    Result = Op.ResNo ? Hi : Low;
-    return;
-  }
   case ISD::SDIV:
   case ISD::UDIV: {
     // FIXME: should use a custom expander to expose the SRA to the dag.
diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td
index 6a1b01255a..3d610635cc 100644
--- a/lib/Target/Sparc/SparcInstrInfo.td
+++ b/lib/Target/Sparc/SparcInstrInfo.td
@@ -453,16 +453,20 @@ def LEA_ADDri   : F3_2<2, 0b000000,
                    
 def ADDCCrr : F3_1<2, 0b010000, 
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
-                   "addcc $b, $c, $dst", []>;
+                   "addcc $b, $c, $dst",
+                   [(set IntRegs:$dst, (addc IntRegs:$b, IntRegs:$c))]>;
 def ADDCCri : F3_2<2, 0b010000,
                    (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
-                   "addcc $b, $c, $dst", []>;
+                   "addcc $b, $c, $dst", 
+                   [(set IntRegs:$dst, (addc IntRegs:$b, simm13:$c))]>;
 def ADDXrr  : F3_1<2, 0b001000, 
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
-                   "addx $b, $c, $dst", []>;
+                   "addx $b, $c, $dst",
+                   [(set IntRegs:$dst, (adde IntRegs:$b, IntRegs:$c))]>;
 def ADDXri  : F3_2<2, 0b001000,
                    (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
-                   "addx $b, $c, $dst", []>;
+                   "addx $b, $c, $dst",
+                   [(set IntRegs:$dst, (adde IntRegs:$b, simm13:$c))]>;
 
 // Section B.15 - Subtract Instructions, p. 110
 def SUBrr   : F3_1<2, 0b000100, 
@@ -475,10 +479,12 @@ def SUBri   : F3_2<2, 0b000100,
                    [(set IntRegs:$dst, (sub IntRegs:$b, simm13:$c))]>;
 def SUBXrr  : F3_1<2, 0b001100, 
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
-                   "subx $b, $c, $dst", []>;
+                   "subx $b, $c, $dst",
+                   [(set IntRegs:$dst, (sube IntRegs:$b, IntRegs:$c))]>;
 def SUBXri  : F3_2<2, 0b001100,
                    (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
-                   "subx $b, $c, $dst", []>;
+                   "subx $b, $c, $dst",
+                   [(set IntRegs:$dst, (sube IntRegs:$b, simm13:$c))]>;
 def SUBCCrr : F3_1<2, 0b010100, 
                    (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
                    "subcc $b, $c, $dst",
@@ -866,6 +872,12 @@ def : Pat<(i32 simm13:$val),
 def : Pat<(i32 imm:$val),
           (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
 
+// subc
+def : Pat<(subc IntRegs:$b, IntRegs:$c),
+          (SUBCCrr IntRegs:$b, IntRegs:$c)>;
+def : Pat<(subc IntRegs:$b, simm13:$val),
+          (SUBCCri IntRegs:$b, imm:$val)>;
+
 // Global addresses, constant pool entries
 def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
 def : Pat<(SPlo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>;