Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30844 91177308-0d34-0410-b5e6-96231b3b80d8

2 files changed, 26 insertions, 26 deletions

diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
index 84bad9a9d1..c92a19bf7e 100644
--- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp
+++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
@@ -330,7 +330,7 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
         SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
         SDOperand Load;
         if (ObjectVT == MVT::i32) {
-          Load = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
+          Load = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
         } else {
           ISD::LoadExtType LoadOp =
             I->getType()->isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
@@ -340,7 +340,7 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
           FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr,
                               DAG.getConstant(Offset, MVT::i32));
           Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr,
-                                DAG.getSrcValue(0), ObjectVT);
+                                NULL, 0, ObjectVT);
           Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load);
         }
         ArgValues.push_back(Load);
@@ -363,7 +363,7 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
       } else {
         int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
         SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
-        SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, DAG.getSrcValue(0));
+        SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, NULL, 0);
         ArgValues.push_back(Load);
       }
       ArgOffset += 4;
@@ -384,8 +384,7 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
         // because the double wouldn't be aligned!
         int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset);
         SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
-        ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, 
-                                        DAG.getSrcValue(0)));
+        ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, NULL, 0));
       } else {
         SDOperand HiVal;
         if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
@@ -395,7 +394,7 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
         } else {
           int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
           SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
-          HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
+          HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
         }
         
         SDOperand LoVal;
@@ -406,7 +405,7 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
         } else {
           int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
           SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
-          LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
+          LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
         }
         
         // Compose the two halves together into an i64 unit.
@@ -794,8 +793,9 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
     MVT::ValueType VT = Node->getValueType(0);
     SDOperand InChain = Node->getOperand(0);
     SDOperand VAListPtr = Node->getOperand(1);
+    SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
     SDOperand VAList = DAG.getLoad(getPointerTy(), InChain, VAListPtr,
-                                   Node->getOperand(2));
+                                   SV->getValue(), SV->getOffset());
     // Increment the pointer, VAList, to the next vaarg
     SDOperand NextPtr = DAG.getNode(ISD::ADD, getPointerTy(), VAList, 
                                     DAG.getConstant(MVT::getSizeInBits(VT)/8, 
@@ -806,10 +806,10 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
     // Load the actual argument out of the pointer VAList, unless this is an
     // f64 load.
     if (VT != MVT::f64) {
-      return DAG.getLoad(VT, InChain, VAList, DAG.getSrcValue(0));
+      return DAG.getLoad(VT, InChain, VAList, NULL, 0);
     } else {
       // Otherwise, load it as i64, then do a bitconvert.
-      SDOperand V = DAG.getLoad(MVT::i64, InChain, VAList, DAG.getSrcValue(0));
+      SDOperand V = DAG.getLoad(MVT::i64, InChain, VAList, NULL, 0);
       std::vector<MVT::ValueType> Tys;
       Tys.push_back(MVT::f64);
       Tys.push_back(MVT::Other);
diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td
index 0137a0d622..6fc4481934 100644
--- a/lib/Target/Sparc/SparcInstrInfo.td
+++ b/lib/Target/Sparc/SparcInstrInfo.td
@@ -278,35 +278,35 @@ let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, noResults = 1 in {
 def LDSBrr : F3_1<3, 0b001001,
                   (ops IntRegs:$dst, MEMrr:$addr),
                   "ldsb [$addr], $dst",
-                  [(set IntRegs:$dst, (sextload ADDRrr:$addr, i8))]>;
+                  [(set IntRegs:$dst, (sextloadi8 ADDRrr:$addr))]>;
 def LDSBri : F3_2<3, 0b001001,
                   (ops IntRegs:$dst, MEMri:$addr),
                   "ldsb [$addr], $dst",
-                  [(set IntRegs:$dst, (sextload ADDRri:$addr, i8))]>;
+                  [(set IntRegs:$dst, (sextloadi8 ADDRri:$addr))]>;
 def LDSHrr : F3_1<3, 0b001010,
                   (ops IntRegs:$dst, MEMrr:$addr),
                   "ldsh [$addr], $dst",
-                  [(set IntRegs:$dst, (sextload ADDRrr:$addr, i16))]>;
+                  [(set IntRegs:$dst, (sextloadi16 ADDRrr:$addr))]>;
 def LDSHri : F3_2<3, 0b001010,
                   (ops IntRegs:$dst, MEMri:$addr),
                   "ldsh [$addr], $dst",
-                  [(set IntRegs:$dst, (sextload ADDRri:$addr, i16))]>;
+                  [(set IntRegs:$dst, (sextloadi16 ADDRri:$addr))]>;
 def LDUBrr : F3_1<3, 0b000001,
                   (ops IntRegs:$dst, MEMrr:$addr),
                   "ldub [$addr], $dst",
-                  [(set IntRegs:$dst, (zextload ADDRrr:$addr, i8))]>;
+                  [(set IntRegs:$dst, (zextloadi8 ADDRrr:$addr))]>;
 def LDUBri : F3_2<3, 0b000001,
                   (ops IntRegs:$dst, MEMri:$addr),
                   "ldub [$addr], $dst",
-                  [(set IntRegs:$dst, (zextload ADDRri:$addr, i8))]>;
+                  [(set IntRegs:$dst, (zextloadi8 ADDRri:$addr))]>;
 def LDUHrr : F3_1<3, 0b000010,
                   (ops IntRegs:$dst, MEMrr:$addr),
                   "lduh [$addr], $dst",
-                  [(set IntRegs:$dst, (zextload ADDRrr:$addr, i16))]>;
+                  [(set IntRegs:$dst, (zextloadi16 ADDRrr:$addr))]>;
 def LDUHri : F3_2<3, 0b000010,
                   (ops IntRegs:$dst, MEMri:$addr),
                   "lduh [$addr], $dst",
-                  [(set IntRegs:$dst, (zextload ADDRri:$addr, i16))]>;
+                  [(set IntRegs:$dst, (zextloadi16 ADDRri:$addr))]>;
 def LDrr   : F3_1<3, 0b000000,
                   (ops IntRegs:$dst, MEMrr:$addr),
                   "ld [$addr], $dst",
@@ -760,16 +760,16 @@ def : Pat<(call texternalsym:$dst),
 def : Pat<(ret), (RETL)>;
 
 // Map integer extload's to zextloads.
-def : Pat<(i32 (extload ADDRrr:$src, i1)), (LDUBrr ADDRrr:$src)>;
-def : Pat<(i32 (extload ADDRri:$src, i1)), (LDUBri ADDRri:$src)>;
-def : Pat<(i32 (extload ADDRrr:$src, i8)), (LDUBrr ADDRrr:$src)>;
-def : Pat<(i32 (extload ADDRri:$src, i8)), (LDUBri ADDRri:$src)>;
-def : Pat<(i32 (extload ADDRrr:$src, i16)), (LDUHrr ADDRrr:$src)>;
-def : Pat<(i32 (extload ADDRri:$src, i16)), (LDUHri ADDRri:$src)>;
+def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
+def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
+def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
+def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>;
+def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>;
+def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>;
 
 // zextload bool -> zextload byte
-def : Pat<(i32 (zextload ADDRrr:$src, i1)), (LDUBrr ADDRrr:$src)>;
-def : Pat<(i32 (zextload ADDRri:$src, i1)), (LDUBri ADDRri:$src)>;
+def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
+def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
 
 // truncstore bool -> truncstore byte.
 def : Pat<(truncstore IntRegs:$src, ADDRrr:$addr, i1),