Fix a bug in i32->f64 conversion lowering

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25211 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 2 insertions, 2 deletions

diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
index a0d6b2ffec..1ef719558a 100644
--- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp
+++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
@@ -622,9 +622,9 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
     return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
   case ISD::SINT_TO_FP: {
     assert(Op.getOperand(0).getValueType() == MVT::i32);
-    Op = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
+    SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
     // Convert the int value to FP in an FP register.
-    return DAG.getNode(V8ISD::ITOF, Op.getValueType(), Op);
+    return DAG.getNode(V8ISD::ITOF, Op.getValueType(), Tmp);
   }
   case ISD::BR_CC: {
     SDOperand Chain = Op.getOperand(0);