diff options
author | Brian Gaeke <gaeke@uiuc.edu> | 2004-02-25 19:28:19 +0000 |
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committer | Brian Gaeke <gaeke@uiuc.edu> | 2004-02-25 19:28:19 +0000 |
commit | e785e531f4495068ee46cabd926939eec15a565a (patch) | |
tree | 45cecabf95d92c9b76bc0f09eb2ce76a2573a973 /lib/Target/Sparc/SparcRegisterInfo.cpp | |
parent | 150666fd82f96a8615e63d3797e2d00f3edcb3e0 (diff) |
SparcV8 skeleton
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11828 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Sparc/SparcRegisterInfo.cpp')
-rw-r--r-- | lib/Target/Sparc/SparcRegisterInfo.cpp | 99 |
1 files changed, 99 insertions, 0 deletions
diff --git a/lib/Target/Sparc/SparcRegisterInfo.cpp b/lib/Target/Sparc/SparcRegisterInfo.cpp new file mode 100644 index 0000000000..d6fd83a4f5 --- /dev/null +++ b/lib/Target/Sparc/SparcRegisterInfo.cpp @@ -0,0 +1,99 @@ +//===- SparcV8RegisterInfo.cpp - SparcV8 Register Information ---*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file was developed by the LLVM research group and is distributed under +// the University of Illinois Open Source License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file contains the SparcV8 implementation of the MRegisterInfo class. +// +//===----------------------------------------------------------------------===// + +#include "SparcV8.h" +#include "SparcV8RegisterInfo.h" +#include "llvm/Type.h" +using namespace llvm; + +SparcV8RegisterInfo::SparcV8RegisterInfo() + : SparcV8GenRegisterInfo(SparcV8::ADJCALLSTACKDOWN, + SparcV8::ADJCALLSTACKUP) {} + +int SparcV8RegisterInfo::storeRegToStackSlot( + MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + unsigned SrcReg, int FrameIdx, + const TargetRegisterClass *RC) const +{ + abort(); + return -1; +} + +int SparcV8RegisterInfo::loadRegFromStackSlot( + MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + unsigned DestReg, int FrameIdx, + const TargetRegisterClass *RC) const +{ + abort(); + return -1; +} + +int SparcV8RegisterInfo::copyRegToReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *RC) const { + abort(); + return -1; +} + +void SparcV8RegisterInfo:: +eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, + MachineBasicBlock::iterator I) const { + abort(); +} + +void +SparcV8RegisterInfo::eliminateFrameIndex(MachineFunction &MF, + MachineBasicBlock::iterator II) const { + abort(); +} + +void SparcV8RegisterInfo::processFunctionBeforeFrameFinalized( + MachineFunction &MF) const { + abort(); +} + +void SparcV8RegisterInfo::emitPrologue(MachineFunction &MF) const { + abort(); +} + +void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF, + MachineBasicBlock &MBB) const { + abort(); +} + + +#include "SparcV8GenRegisterInfo.inc" + +const TargetRegisterClass* +SparcV8RegisterInfo::getRegClassForType(const Type* Ty) const { + switch (Ty->getPrimitiveID()) { + case Type::LongTyID: + case Type::ULongTyID: assert(0 && "Long values can't fit in registers!"); + default: assert(0 && "Invalid type to getClass!"); + case Type::BoolTyID: + case Type::SByteTyID: + case Type::UByteTyID: + case Type::ShortTyID: + case Type::UShortTyID: + case Type::IntTyID: + case Type::UIntTyID: + case Type::PointerTyID: return &GPRCInstance; + + case Type::FloatTyID: + case Type::DoubleTyID: return &FPRCInstance; + } +} + |