diff options
author | Chris Lattner <sabre@nondot.org> | 2005-12-17 20:18:49 +0000 |
---|---|---|
committer | Chris Lattner <sabre@nondot.org> | 2005-12-17 20:18:49 +0000 |
commit | 331355cf7da6613ff86732550ccc1d32ee1dce61 (patch) | |
tree | 0a42220c4700b27f4cede493e38d88a9d15a61cf /lib/Target/Sparc/SparcRegisterInfo.cpp | |
parent | 84e2abf116c236d9493995e65259f1352a925239 (diff) |
Rename load/store instructions to include an RI suffix
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24784 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Sparc/SparcRegisterInfo.cpp')
-rw-r--r-- | lib/Target/Sparc/SparcRegisterInfo.cpp | 11 |
1 files changed, 4 insertions, 7 deletions
diff --git a/lib/Target/Sparc/SparcRegisterInfo.cpp b/lib/Target/Sparc/SparcRegisterInfo.cpp index af8605a682..0c6015f190 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.cpp +++ b/lib/Target/Sparc/SparcRegisterInfo.cpp @@ -41,12 +41,10 @@ static const TargetRegisterClass *getClass(unsigned SrcReg) { void SparcV8RegisterInfo:: storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned SrcReg, int FrameIdx, - const TargetRegisterClass *rc) const { - const TargetRegisterClass *RC = getClass(SrcReg); - + const TargetRegisterClass *RC) const { // On the order of operands here: think "[FrameIdx + 0] = SrcReg". if (RC == V8::IntRegsRegisterClass) - BuildMI (MBB, I, V8::ST, 3).addFrameIndex (FrameIdx).addSImm (0) + BuildMI (MBB, I, V8::STri, 3).addFrameIndex (FrameIdx).addSImm (0) .addReg (SrcReg); else if (RC == V8::FPRegsRegisterClass) BuildMI (MBB, I, V8::STFri, 3).addFrameIndex (FrameIdx).addSImm (0) @@ -61,10 +59,9 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, void SparcV8RegisterInfo:: loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned DestReg, int FrameIdx, - const TargetRegisterClass *rc) const { - const TargetRegisterClass *RC = getClass(DestReg); + const TargetRegisterClass *RC) const { if (RC == V8::IntRegsRegisterClass) - BuildMI (MBB, I, V8::LD, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0); + BuildMI (MBB, I, V8::LDri, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0); else if (RC == V8::FPRegsRegisterClass) BuildMI (MBB, I, V8::LDFri, 2, DestReg).addFrameIndex (FrameIdx) .addSImm (0); |