aboutsummaryrefslogtreecommitdiff
path: root/lib/Target/Sparc/SparcISelLowering.cpp
diff options
context:
space:
mode:
authorVenkatraman Govindaraju <venkatra@cs.wisc.edu>2011-01-21 22:00:00 +0000
committerVenkatraman Govindaraju <venkatra@cs.wisc.edu>2011-01-21 22:00:00 +0000
commitfc3faa75cbadd8a1020941ec85adfda1d2f49688 (patch)
treec9aa42076f7c52f339b282b98918bad113c98643 /lib/Target/Sparc/SparcISelLowering.cpp
parent5d2e1889622cc20ada6146041e6d862a6588194f (diff)
Sparc backend:
Rename FLUSH to FLUSHW. Output "ta 3" instead of a "flushw" instruction if v8 instruction set is used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123997 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Sparc/SparcISelLowering.cpp')
-rw-r--r--lib/Target/Sparc/SparcISelLowering.cpp32
1 files changed, 16 insertions, 16 deletions
diff --git a/lib/Target/Sparc/SparcISelLowering.cpp b/lib/Target/Sparc/SparcISelLowering.cpp
index f78d5fa507..2767862dc3 100644
--- a/lib/Target/Sparc/SparcISelLowering.cpp
+++ b/lib/Target/Sparc/SparcISelLowering.cpp
@@ -721,7 +721,7 @@ const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
case SPISD::CALL: return "SPISD::CALL";
case SPISD::RET_FLAG: return "SPISD::RET_FLAG";
case SPISD::GLOBAL_BASE_REG: return "SPISD::GLOBAL_BASE_REG";
- case SPISD::FLUSH: return "SPISD::FLUSH";
+ case SPISD::FLUSHW: return "SPISD::FLUSHW";
}
}
@@ -969,9 +969,9 @@ static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) {
}
-static SDValue getFLUSH(SDValue Op, SelectionDAG &DAG) {
+static SDValue getFLUSHW(SDValue Op, SelectionDAG &DAG) {
DebugLoc dl = Op.getDebugLoc();
- SDValue Chain = DAG.getNode(SPISD::FLUSH,
+ SDValue Chain = DAG.getNode(SPISD::FLUSHW,
dl, MVT::Other, DAG.getEntryNode());
return Chain;
}
@@ -987,19 +987,19 @@ static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
uint64_t depth = Op.getConstantOperandVal(0);
SDValue FrameAddr;
- if (depth == 0)
+ if (depth == 0)
FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
else {
// flush first to make sure the windowed registers' values are in stack
- SDValue Chain = getFLUSH(Op, DAG);
+ SDValue Chain = getFLUSHW(Op, DAG);
FrameAddr = DAG.getCopyFromReg(Chain, dl, FrameReg, VT);
-
+
for (uint64_t i = 0; i != depth; ++i) {
- SDValue Ptr = DAG.getNode(ISD::ADD,
+ SDValue Ptr = DAG.getNode(ISD::ADD,
dl, MVT::i32,
FrameAddr, DAG.getIntPtrConstant(56));
- FrameAddr = DAG.getLoad(MVT::i32, dl,
- Chain,
+ FrameAddr = DAG.getLoad(MVT::i32, dl,
+ Chain,
Ptr,
MachinePointerInfo(), false, false, 0);
}
@@ -1018,20 +1018,20 @@ static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
uint64_t depth = Op.getConstantOperandVal(0);
SDValue RetAddr;
- if (depth == 0)
+ if (depth == 0)
RetAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, RetReg, VT);
else {
// flush first to make sure the windowed registers' values are in stack
- SDValue Chain = getFLUSH(Op, DAG);
+ SDValue Chain = getFLUSHW(Op, DAG);
RetAddr = DAG.getCopyFromReg(Chain, dl, SP::I6, VT);
-
+
for (uint64_t i = 0; i != depth; ++i) {
- SDValue Ptr = DAG.getNode(ISD::ADD,
+ SDValue Ptr = DAG.getNode(ISD::ADD,
dl, MVT::i32,
- RetAddr,
+ RetAddr,
DAG.getIntPtrConstant((i == depth-1)?60:56));
- RetAddr = DAG.getLoad(MVT::i32, dl,
- Chain,
+ RetAddr = DAG.getLoad(MVT::i32, dl,
+ Chain,
Ptr,
MachinePointerInfo(), false, false, 0);
}