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| author | Misha Brukman <brukman+llvm@gmail.com> | 2004-06-24 21:56:15 +0000 |
|---|---|---|
| committer | Misha Brukman <brukman+llvm@gmail.com> | 2004-06-24 21:56:15 +0000 |
| commit | 1916bf942746b4f41312ce287329af3c6ec8bf6f (patch) | |
| tree | 20723489fd8c53e33c556dfb4a1003700940f857 /lib/Target/PowerPC/PowerPCISelSimple.cpp | |
| parent | 98649d17966f3c32d2f67c16ec2a6183748bb243 (diff) | |
Unindent some code, it only needs 2 spaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14376 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PowerPCISelSimple.cpp')
| -rw-r--r-- | lib/Target/PowerPC/PowerPCISelSimple.cpp | 46 |
1 files changed, 23 insertions, 23 deletions
diff --git a/lib/Target/PowerPC/PowerPCISelSimple.cpp b/lib/Target/PowerPC/PowerPCISelSimple.cpp index 33f979dac6..d9c3ff5985 100644 --- a/lib/Target/PowerPC/PowerPCISelSimple.cpp +++ b/lib/Target/PowerPC/PowerPCISelSimple.cpp @@ -1247,32 +1247,32 @@ void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI, case cFP: ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg; if (Args[i].Ty == Type::FloatTy) { - // Reg or stack? - if (FPR_remaining > 0) { - BuildMI(BB, PPC32::FMR, 1, PPC32::F0 + FPR_idx).addReg(ArgReg); - FPR_remaining--; - FPR_idx++; - } else { - BuildMI(BB, PPC32::STFS, 3).addReg(ArgReg).addImm(ArgOffset) - .addReg(PPC32::R1); - } + // Reg or stack? + if (FPR_remaining > 0) { + BuildMI(BB, PPC32::FMR, 1, PPC32::F0 + FPR_idx).addReg(ArgReg); + FPR_remaining--; + FPR_idx++; + } else { + BuildMI(BB, PPC32::STFS, 3).addReg(ArgReg).addImm(ArgOffset) + .addReg(PPC32::R1); + } } else { assert(Args[i].Ty == Type::DoubleTy && "Unknown FP type!"); - // Reg or stack? - if (FPR_remaining > 0) { - BuildMI(BB, PPC32::FMR, 1, PPC32::F0 + FPR_idx).addReg(ArgReg); - FPR_remaining--; - FPR_idx++; - } else { - BuildMI(BB, PPC32::STFD, 3).addReg(ArgReg).addImm(ArgOffset) - .addReg(PPC32::R1); - } + // Reg or stack? + if (FPR_remaining > 0) { + BuildMI(BB, PPC32::FMR, 1, PPC32::F0 + FPR_idx).addReg(ArgReg); + FPR_remaining--; + FPR_idx++; + } else { + BuildMI(BB, PPC32::STFD, 3).addReg(ArgReg).addImm(ArgOffset) + .addReg(PPC32::R1); + } - ArgOffset += 4; // 8 byte entry, not 4. - if (GPR_remaining > 0) { - GPR_remaining--; // uses up 2 GPRs - GPR_idx++; - } + ArgOffset += 4; // 8 byte entry, not 4. + if (GPR_remaining > 0) { + GPR_remaining--; // uses up 2 GPRs + GPR_idx++; + } } break; |