Disable switch lowering for targets based on the selection dag isel,

letting the code generator handle them directly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27539 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 0 insertions, 6 deletions

diff --git a/lib/Target/PowerPC/PPCTargetMachine.cpp b/lib/Target/PowerPC/PPCTargetMachine.cpp
index 60829560a3..94136a4569 100644
--- a/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ b/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -93,9 +93,6 @@ bool PPCTargetMachine::addPassesToEmitFile(PassManager &PM,
   // Clean up after other passes, e.g. merging critical edges.
   if (!Fast) PM.add(createCFGSimplificationPass());
 
-  // FIXME: Implement the switch instruction in the instruction selector!
-  PM.add(createLowerSwitchPass());
-
   // Make sure that no unreachable blocks are instruction selected.
   PM.add(createUnreachableBlockEliminationPass());
 
@@ -147,9 +144,6 @@ void PPCJITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
   // Clean up after other passes, e.g. merging critical edges.
   PM.add(createCFGSimplificationPass());
 
-  // FIXME: Implement the switch instruction in the instruction selector!
-  PM.add(createLowerSwitchPass());
-
   // Make sure that no unreachable blocks are instruction selected.
   PM.add(createUnreachableBlockEliminationPass());