Move some more instruction creation methods from RegisterInfo into InstrInfo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45484 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 0 insertions, 228 deletions

diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 173b29e5b4..0dc4ed2741 100644
--- a/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -104,234 +104,6 @@ PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
   ImmToIdxMap[PPC::ADDI8] = PPC::ADD8; ImmToIdxMap[PPC::STD_32] = PPC::STDX_32;
 }
 
-static void StoreRegToStackSlot(const TargetInstrInfo &TII,
-                                unsigned SrcReg, bool isKill, int FrameIdx,
-                                const TargetRegisterClass *RC,
-                                SmallVectorImpl<MachineInstr*> &NewMIs) {
-  if (RC == PPC::GPRCRegisterClass) {
-    if (SrcReg != PPC::LR) {
-      NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW))
-                                .addReg(SrcReg, false, false, isKill), FrameIdx));
-    } else {
-      // FIXME: this spills LR immediately to memory in one step.  To do this,
-      // we use R11, which we know cannot be used in the prolog/epilog.  This is
-      // a hack.
-      NewMIs.push_back(BuildMI(TII.get(PPC::MFLR), PPC::R11));
-      NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW))
-                              .addReg(PPC::R11, false, false, isKill), FrameIdx));
-    }
-  } else if (RC == PPC::G8RCRegisterClass) {
-    if (SrcReg != PPC::LR8) {
-      NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STD))
-                                .addReg(SrcReg, false, false, isKill), FrameIdx));
-    } else {
-      // FIXME: this spills LR immediately to memory in one step.  To do this,
-      // we use R11, which we know cannot be used in the prolog/epilog.  This is
-      // a hack.
-      NewMIs.push_back(BuildMI(TII.get(PPC::MFLR8), PPC::X11));
-      NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STD))
-                              .addReg(PPC::X11, false, false, isKill), FrameIdx));
-    }
-  } else if (RC == PPC::F8RCRegisterClass) {
-    NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STFD))
-                                .addReg(SrcReg, false, false, isKill), FrameIdx));
-  } else if (RC == PPC::F4RCRegisterClass) {
-    NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STFS))
-                                .addReg(SrcReg, false, false, isKill), FrameIdx));
-  } else if (RC == PPC::CRRCRegisterClass) {
-    // FIXME: We use R0 here, because it isn't available for RA.
-    // We need to store the CR in the low 4-bits of the saved value.  First,
-    // issue a MFCR to save all of the CRBits.
-    NewMIs.push_back(BuildMI(TII.get(PPC::MFCR), PPC::R0));
-    
-    // If the saved register wasn't CR0, shift the bits left so that they are in
-    // CR0's slot.
-    if (SrcReg != PPC::CR0) {
-      unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
-      // rlwinm r0, r0, ShiftBits, 0, 31.
-      NewMIs.push_back(BuildMI(TII.get(PPC::RLWINM), PPC::R0)
-                       .addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31));
-    }
-    
-    NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::STW))
-                               .addReg(PPC::R0, false, false, isKill), FrameIdx));
-  } else if (RC == PPC::VRRCRegisterClass) {
-    // We don't have indexed addressing for vector loads.  Emit:
-    // R0 = ADDI FI#
-    // STVX VAL, 0, R0
-    // 
-    // FIXME: We use R0 here, because it isn't available for RA.
-    NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::ADDI), PPC::R0),
-                                       FrameIdx, 0, 0));
-    NewMIs.push_back(BuildMI(TII.get(PPC::STVX))
-           .addReg(SrcReg, false, false, isKill).addReg(PPC::R0).addReg(PPC::R0));
-  } else {
-    assert(0 && "Unknown regclass!");
-    abort();
-  }
-}
-
-void
-PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
-                                     MachineBasicBlock::iterator MI,
-                                     unsigned SrcReg, bool isKill, int FrameIdx,
-                                     const TargetRegisterClass *RC) const {
-  SmallVector<MachineInstr*, 4> NewMIs;
-  StoreRegToStackSlot(TII, SrcReg, isKill, FrameIdx, RC, NewMIs);
-  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
-    MBB.insert(MI, NewMIs[i]);
-}
-
-void PPCRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
-                                     bool isKill,
-                                     SmallVectorImpl<MachineOperand> &Addr,
-                                     const TargetRegisterClass *RC,
-                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
-  if (Addr[0].isFrameIndex()) {
-    StoreRegToStackSlot(TII, SrcReg, isKill, Addr[0].getIndex(), RC, NewMIs);
-    return;
-  }
-
-  unsigned Opc = 0;
-  if (RC == PPC::GPRCRegisterClass) {
-    Opc = PPC::STW;
-  } else if (RC == PPC::G8RCRegisterClass) {
-    Opc = PPC::STD;
-  } else if (RC == PPC::F8RCRegisterClass) {
-    Opc = PPC::STFD;
-  } else if (RC == PPC::F4RCRegisterClass) {
-    Opc = PPC::STFS;
-  } else if (RC == PPC::VRRCRegisterClass) {
-    Opc = PPC::STVX;
-  } else {
-    assert(0 && "Unknown regclass!");
-    abort();
-  }
-  MachineInstrBuilder MIB = BuildMI(TII.get(Opc))
-    .addReg(SrcReg, false, false, isKill);
-  for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
-    MachineOperand &MO = Addr[i];
-    if (MO.isRegister())
-      MIB.addReg(MO.getReg());
-    else if (MO.isImmediate())
-      MIB.addImm(MO.getImm());
-    else
-      MIB.addFrameIndex(MO.getIndex());
-  }
-  NewMIs.push_back(MIB);
-  return;
-}
-
-static void LoadRegFromStackSlot(const TargetInstrInfo &TII,
-                                 unsigned DestReg, int FrameIdx,
-                                 const TargetRegisterClass *RC,
-                                 SmallVectorImpl<MachineInstr*> &NewMIs) {
-  if (RC == PPC::GPRCRegisterClass) {
-    if (DestReg != PPC::LR) {
-      NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LWZ), DestReg),
-                                         FrameIdx));
-    } else {
-      NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LWZ), PPC::R11),
-                                         FrameIdx));
-      NewMIs.push_back(BuildMI(TII.get(PPC::MTLR)).addReg(PPC::R11));
-    }
-  } else if (RC == PPC::G8RCRegisterClass) {
-    if (DestReg != PPC::LR8) {
-      NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LD), DestReg),
-                                         FrameIdx));
-    } else {
-      NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LD), PPC::R11),
-                                         FrameIdx));
-      NewMIs.push_back(BuildMI(TII.get(PPC::MTLR8)).addReg(PPC::R11));
-    }
-  } else if (RC == PPC::F8RCRegisterClass) {
-    NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LFD), DestReg),
-                                       FrameIdx));
-  } else if (RC == PPC::F4RCRegisterClass) {
-    NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LFS), DestReg),
-                                       FrameIdx));
-  } else if (RC == PPC::CRRCRegisterClass) {
-    // FIXME: We use R0 here, because it isn't available for RA.
-    NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::LWZ), PPC::R0),
-                                       FrameIdx));
-    
-    // If the reloaded register isn't CR0, shift the bits right so that they are
-    // in the right CR's slot.
-    if (DestReg != PPC::CR0) {
-      unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
-      // rlwinm r11, r11, 32-ShiftBits, 0, 31.
-      NewMIs.push_back(BuildMI(TII.get(PPC::RLWINM), PPC::R0)
-                    .addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31));
-    }
-    
-    NewMIs.push_back(BuildMI(TII.get(PPC::MTCRF), DestReg).addReg(PPC::R0));
-  } else if (RC == PPC::VRRCRegisterClass) {
-    // We don't have indexed addressing for vector loads.  Emit:
-    // R0 = ADDI FI#
-    // Dest = LVX 0, R0
-    // 
-    // FIXME: We use R0 here, because it isn't available for RA.
-    NewMIs.push_back(addFrameReference(BuildMI(TII.get(PPC::ADDI), PPC::R0),
-                                       FrameIdx, 0, 0));
-    NewMIs.push_back(BuildMI(TII.get(PPC::LVX),DestReg).addReg(PPC::R0)
-                     .addReg(PPC::R0));
-  } else {
-    assert(0 && "Unknown regclass!");
-    abort();
-  }
-}
-
-void
-PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
-                                      MachineBasicBlock::iterator MI,
-                                      unsigned DestReg, int FrameIdx,
-                                      const TargetRegisterClass *RC) const {
-  SmallVector<MachineInstr*, 4> NewMIs;
-  LoadRegFromStackSlot(TII, DestReg, FrameIdx, RC, NewMIs);
-  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
-    MBB.insert(MI, NewMIs[i]);
-}
-
-void PPCRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
-                                      SmallVectorImpl<MachineOperand> &Addr,
-                                      const TargetRegisterClass *RC,
-                                  SmallVectorImpl<MachineInstr*> &NewMIs) const{
-  if (Addr[0].isFrameIndex()) {
-    LoadRegFromStackSlot(TII, DestReg, Addr[0].getIndex(), RC, NewMIs);
-    return;
-  }
-
-  unsigned Opc = 0;
-  if (RC == PPC::GPRCRegisterClass) {
-    assert(DestReg != PPC::LR && "Can't handle this yet!");
-    Opc = PPC::LWZ;
-  } else if (RC == PPC::G8RCRegisterClass) {
-    assert(DestReg != PPC::LR8 && "Can't handle this yet!");
-    Opc = PPC::LD;
-  } else if (RC == PPC::F8RCRegisterClass) {
-    Opc = PPC::LFD;
-  } else if (RC == PPC::F4RCRegisterClass) {
-    Opc = PPC::LFS;
-  } else if (RC == PPC::VRRCRegisterClass) {
-    Opc = PPC::LVX;
-  } else {
-    assert(0 && "Unknown regclass!");
-    abort();
-  }
-  MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg);
-  for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
-    MachineOperand &MO = Addr[i];
-    if (MO.isRegister())
-      MIB.addReg(MO.getReg());
-    else if (MO.isImmediate())
-      MIB.addImm(MO.getImm());
-    else
-      MIB.addFrameIndex(MO.getIndex());
-  }
-  NewMIs.push_back(MIB);
-  return;
-}
-
 void PPCRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
                                     MachineBasicBlock::iterator I,
                                     unsigned DestReg,