diff options
| author | Chris Lattner <sabre@nondot.org> | 2006-05-04 16:56:45 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2006-05-04 16:56:45 +0000 |
| commit | e45aa737ba902a5caf2f259b3116bfc7d29b2990 (patch) | |
| tree | 0962db070a5fc565f99439fb09f29c838f13f749 /lib/Target/PowerPC/PPCRegisterInfo.cpp | |
| parent | 10efcfabf1970c9fcd1cf357db5e2ff6d6e8efba (diff) | |
Revert Nate's CR patch from last night, which caused many regressions (e.g. fhourstones).
Loading and storing off R0 isn't what we wanted. Also, taking some CR's out of
CRRC seems to cause failures as well. Further investigation is required.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28097 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCRegisterInfo.cpp')
| -rw-r--r-- | lib/Target/PowerPC/PPCRegisterInfo.cpp | 14 |
1 files changed, 6 insertions, 8 deletions
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp index 5fe22adc8a..1f95f49192 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -102,9 +102,8 @@ PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11); addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx); } else if (RC == PPC::CRRCRegisterClass) { - // FIXME: We use R0 here, because it isn't available for RA. - BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R0); - addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R0), FrameIdx); + BuildMI(MBB, MI, PPC::MFCR, 0, PPC::R11); + addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx); } else if (RC == PPC::GPRCRegisterClass) { addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(SrcReg),FrameIdx); } else if (RC == PPC::G8RCRegisterClass) { @@ -119,7 +118,7 @@ PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, // Dest = LVX R0, R11 // // FIXME: We use R0 here, because it isn't available for RA. - addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 2, PPC::R0), FrameIdx, 0, 0); + addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0); BuildMI(MBB, MI, PPC::STVX, 3) .addReg(SrcReg).addReg(PPC::R0).addReg(PPC::R0); } else { @@ -137,9 +136,8 @@ PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx); BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11); } else if (RC == PPC::CRRCRegisterClass) { - // FIXME: We use R0 here, because it isn't available for RA. - addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R0), FrameIdx); - BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R0); + addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx); + BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R11); } else if (RC == PPC::GPRCRegisterClass) { addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, DestReg), FrameIdx); } else if (RC == PPC::G8RCRegisterClass) { @@ -154,7 +152,7 @@ PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, // Dest = LVX R0, R11 // // FIXME: We use R0 here, because it isn't available for RA. - addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 2, PPC::R0), FrameIdx, 0, 0); + addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0); BuildMI(MBB, MI, PPC::LVX, 2, DestReg).addReg(PPC::R0).addReg(PPC::R0); } else { assert(0 && "Unknown regclass!"); |