diff options
| author | Chris Lattner <sabre@nondot.org> | 2006-06-20 23:18:58 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2006-06-20 23:18:58 +0000 |
| commit | b410dc99774d52b4491750dab10b91cca1d661d8 (patch) | |
| tree | 4f46400db189906a9ce7d35a2637f6c348030fb5 /lib/Target/PowerPC/PPCRegisterInfo.cpp | |
| parent | 96dc5e5f6d2bdad7b24f191998e324888afacf83 (diff) | |
Rename OR4 -> OR. Move some PPC64-specific stuff to the 64-bit file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28889 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCRegisterInfo.cpp')
| -rw-r--r-- | lib/Target/PowerPC/PPCRegisterInfo.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp index 8cc2da52fd..41e95a338a 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -189,7 +189,7 @@ void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB, unsigned DestReg, unsigned SrcReg, const TargetRegisterClass *RC) const { if (RC == PPC::GPRCRegisterClass) { - BuildMI(MBB, MI, PPC::OR4, 2, DestReg).addReg(SrcReg).addReg(SrcReg); + BuildMI(MBB, MI, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg); } else if (RC == PPC::G8RCRegisterClass) { BuildMI(MBB, MI, PPC::OR8, 2, DestReg).addReg(SrcReg).addReg(SrcReg); } else if (RC == PPC::F4RCRegisterClass) { @@ -282,7 +282,7 @@ MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI, // it takes more than one instruction to store it. unsigned Opc = MI->getOpcode(); - if ((Opc == PPC::OR4 && + if ((Opc == PPC::OR && MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) { if (OpNum == 0) { // move -> store unsigned InReg = MI->getOperand(1).getReg(); @@ -631,7 +631,7 @@ void PPCRegisterInfo::emitPrologue(MachineFunction &MF) const { if (HasFP) { BuildMI(MBB, MBBI, PPC::STW, 3) .addReg(PPC::R31).addImm(GPRSize).addReg(PPC::R1); - BuildMI(MBB, MBBI, PPC::OR4, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1); + BuildMI(MBB, MBBI, PPC::OR, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1); } } |