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authorHal Finkel <hfinkel@anl.gov>2011-11-22 16:21:04 +0000
committerHal Finkel <hfinkel@anl.gov>2011-11-22 16:21:04 +0000
commit768c65f677af3f05c2e94982043f90a1bfaceda5 (patch)
tree4e16ba3e65d2a908780a7c290cc12512b95de8e7 /lib/Target/PowerPC/PPCInstrInfo.cpp
parent796c193768547459cd6cbd667c8a43fedd601022 (diff)
add basic PPC register-pressure feedback; adjust the vaarg test to match the new register-allocation pattern
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145065 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCInstrInfo.cpp')
-rw-r--r--lib/Target/PowerPC/PPCInstrInfo.cpp7
1 files changed, 2 insertions, 5 deletions
diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp
index 644b20c373..b9a629752b 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -56,11 +56,8 @@ ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetHazardRecognizer(
unsigned Directive = TM->getSubtarget<PPCSubtarget>().getDarwinDirective();
if (Directive == PPC::DIR_440) {
- // Disable the hazard recognizer for now, as it doesn't support
- // bottom-up scheduling.
- //const InstrItineraryData *II = TM->getInstrItineraryData();
- //return new PPCHazardRecognizer440(II, DAG);
- return new ScheduleHazardRecognizer();
+ const InstrItineraryData *II = TM->getInstrItineraryData();
+ return new PPCHazardRecognizer440(II, DAG);
}
else {
// Disable the hazard recognizer for now, as it doesn't support