diff options
| author | Chris Lattner <sabre@nondot.org> | 2005-04-13 02:40:26 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2005-04-13 02:40:26 +0000 |
| commit | c951d87fe99ab464b933af7170de6f2e51953907 (patch) | |
| tree | d05f8550a98450afba5ff306434872cc5753334d /lib/Target/PowerPC/PPCISelPattern.cpp | |
| parent | 91302a10aeb1273c33bbac756b9fd3e7095859f3 (diff) | |
Elimate handling of ZERO_EXTEND_INREG. This causes the PPC backend to emit
andi instructions instead of rlwinm instructions for zero extend, but they
seem like they would take the same time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21268 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCISelPattern.cpp')
| -rw-r--r-- | lib/Target/PowerPC/PPCISelPattern.cpp | 13 |
1 files changed, 0 insertions, 13 deletions
diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp index a2b1e739bd..1e4b88f5b4 100644 --- a/lib/Target/PowerPC/PPCISelPattern.cpp +++ b/lib/Target/PowerPC/PPCISelPattern.cpp @@ -1636,19 +1636,6 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) { } return Result; - case ISD::ZERO_EXTEND_INREG: - Tmp1 = SelectExpr(N.getOperand(0)); - switch(cast<MVTSDNode>(Node)->getExtraValueType()) { - default: Node->dump(); assert(0 && "Unhandled ZERO_EXTEND type"); break; - case MVT::i16: Tmp2 = 16; break; - case MVT::i8: Tmp2 = 24; break; - case MVT::i1: Tmp2 = 31; break; - } - Opc = Recording ? PPC::RLWINMo : PPC::RLWINM; - RecordSuccess = true; - BuildMI(BB, Opc, 4, Result).addReg(Tmp1).addImm(0).addImm(Tmp2).addImm(31); - return Result; - case ISD::CopyFromReg: if (Result == 1) Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType()); |