Remove trailing whitespace

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21425 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 135 insertions, 135 deletions

diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp
index 423eafe68f..84c05cb637 100644
--- a/lib/Target/PowerPC/PPCISelPattern.cpp
+++ b/lib/Target/PowerPC/PPCISelPattern.cpp
@@ -4,7 +4,7 @@
 //
 // This file was developed by Nate Begeman and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file defines a pattern matching instruction selector for 32 bit PowerPC.
@@ -47,7 +47,7 @@ namespace {
       addRegisterClass(MVT::i32, PPC32::GPRCRegisterClass);
       addRegisterClass(MVT::f32, PPC32::FPRCRegisterClass);
       addRegisterClass(MVT::f64, PPC32::FPRCRegisterClass);
-      
+
       // PowerPC has no intrinsics for these particular operations
       setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
       setOperationAction(ISD::MEMSET, MVT::Other, Expand);
@@ -56,14 +56,14 @@ namespace {
       // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
       setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
       setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
-      
+
       // PowerPC has no SREM/UREM instructions
       setOperationAction(ISD::SREM, MVT::i32, Expand);
       setOperationAction(ISD::UREM, MVT::i32, Expand);
 
       setSetCCResultContents(ZeroOrOneSetCCResult);
       addLegalFPImmediate(+0.0); // Necessary for FSEL
-      addLegalFPImmediate(-0.0); // 
+      addLegalFPImmediate(-0.0); //
 
       computeRegisterProperties();
     }
@@ -72,16 +72,16 @@ namespace {
     /// lower the arguments for the specified function, into the specified DAG.
     virtual std::vector<SDOperand>
     LowerArguments(Function &F, SelectionDAG &DAG);
-    
+
     /// LowerCallTo - This hook lowers an abstract call to a function into an
     /// actual call.
     virtual std::pair<SDOperand, SDOperand>
     LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
                 SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG);
-    
+
     virtual std::pair<SDOperand, SDOperand>
     LowerVAStart(SDOperand Chain, SelectionDAG &DAG);
-    
+
     virtual std::pair<SDOperand,SDOperand>
     LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
                    const Type *ArgTy, SelectionDAG &DAG);
@@ -102,8 +102,8 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
   MachineFrameInfo *MFI = MF.getFrameInfo();
   MachineBasicBlock& BB = MF.front();
   std::vector<SDOperand> ArgValues;
-  
-  // Due to the rather complicated nature of the PowerPC ABI, rather than a 
+
+  // Due to the rather complicated nature of the PowerPC ABI, rather than a
   // fixed size array of physical args, for the sake of simplicity let the STL
   // handle tracking them for us.
   std::vector<unsigned> argVR, argPR, argOp;
@@ -111,7 +111,7 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
   unsigned GPR_remaining = 8;
   unsigned FPR_remaining = 13;
   unsigned GPR_idx = 0, FPR_idx = 0;
-  static const unsigned GPR[] = { 
+  static const unsigned GPR[] = {
     PPC::R3, PPC::R4, PPC::R5, PPC::R6,
     PPC::R7, PPC::R8, PPC::R9, PPC::R10,
   };
@@ -129,13 +129,13 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
     bool needsLoad = false;
     bool ArgLive = !I->use_empty();
     MVT::ValueType ObjectVT = getValueType(I->getType());
-    
+
     switch (ObjectVT) {
     default: assert(0 && "Unhandled argument type!");
     case MVT::i1:
     case MVT::i8:
     case MVT::i16:
-    case MVT::i32: 
+    case MVT::i32:
       ObjSize = 4;
       if (!ArgLive) break;
       if (GPR_remaining > 0) {
@@ -170,7 +170,7 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
         argt = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, argLo, argHi);
         newroot = argLo;
       } else {
-        needsLoad = true; 
+        needsLoad = true;
       }
       break;
       case MVT::f32:
@@ -179,7 +179,7 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
       if (!ArgLive) break;
       if (FPR_remaining > 0) {
         MF.addLiveIn(FPR[FPR_idx]);
-        argt = newroot = DAG.getCopyFromReg(FPR[FPR_idx], ObjectVT, 
+        argt = newroot = DAG.getCopyFromReg(FPR[FPR_idx], ObjectVT,
                                             DAG.getRoot());
         --FPR_remaining;
         ++FPR_idx;
@@ -188,20 +188,20 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
       }
       break;
     }
-    
+
     // We need to load the argument to a virtual register if we determined above
-    // that we ran out of physical registers of the appropriate type 
+    // that we ran out of physical registers of the appropriate type
     if (needsLoad) {
       unsigned SubregOffset = 0;
       if (ObjectVT == MVT::i8 || ObjectVT == MVT::i1) SubregOffset = 3;
       if (ObjectVT == MVT::i16) SubregOffset = 2;
       int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
       SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
-      FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, 
+      FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN,
                         DAG.getConstant(SubregOffset, MVT::i32));
       argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN);
     }
-    
+
     // Every 4 bytes of argument space consumes one of the GPRs available for
     // argument passing.
     if (GPR_remaining > 0) {
@@ -212,7 +212,7 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
     ArgOffset += ObjSize;
     if (newroot.Val)
       DAG.setRoot(newroot.getValue(1));
-    
+
     ArgValues.push_back(argt);
   }
 
@@ -228,7 +228,7 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
     for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) {
       MF.addLiveIn(GPR[GPR_idx]);
       SDOperand Val = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i32, DAG.getRoot());
-      SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1), 
+      SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
                                     Val, FIN);
       MemOps.push_back(Store);
       // Increment the address by four for the next argument to store
@@ -292,8 +292,8 @@ PPC32TargetLowering::LowerCallTo(SDOperand Chain,
         NumBytes += 8;
         break;
       }
-    
-    // Just to be safe, we'll always reserve the full 24 bytes of linkage area 
+
+    // Just to be safe, we'll always reserve the full 24 bytes of linkage area
     // plus 32 bytes of argument space in case any called code gets funky on us.
     if (NumBytes < 56) NumBytes = 56;
 
@@ -307,7 +307,7 @@ PPC32TargetLowering::LowerCallTo(SDOperand Chain,
     // passing.
     SDOperand StackPtr = DAG.getCopyFromReg(PPC::R1, MVT::i32,
                                             DAG.getEntryNode());
-    
+
     // Figure out which arguments are going to go in registers, and which in
     // memory.  Also, if this is a vararg function, floating point operations
     // must be stored to our stack, and loaded into integer regs as well, if
@@ -315,7 +315,7 @@ PPC32TargetLowering::LowerCallTo(SDOperand Chain,
     unsigned ArgOffset = 24;
     unsigned GPR_remaining = 8;
     unsigned FPR_remaining = 13;
-    
+
     std::vector<SDOperand> MemOps;
     for (unsigned i = 0, e = Args.size(); i != e; ++i) {
       // PtrOff will be used to store the current argument to the stack if a
@@ -323,7 +323,7 @@ PPC32TargetLowering::LowerCallTo(SDOperand Chain,
       SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
       PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
       MVT::ValueType ArgVT = getValueType(Args[i].second);
-      
+
       switch (ArgVT) {
       default: assert(0 && "Unexpected ValueType for argument!");
       case MVT::i1:
@@ -351,9 +351,9 @@ PPC32TargetLowering::LowerCallTo(SDOperand Chain,
         // in it, and store the other half to the stack.  If we have two or more
         // free GPRs, then we can pass both halves of the i64 in registers.
         if (GPR_remaining > 0) {
-          SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, 
+          SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
             Args[i].first, DAG.getConstant(1, MVT::i32));
-          SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, 
+          SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
             Args[i].first, DAG.getConstant(0, MVT::i32));
           args_to_use.push_back(Hi);
           --GPR_remaining;
@@ -420,14 +420,14 @@ PPC32TargetLowering::LowerCallTo(SDOperand Chain,
     if (!MemOps.empty())
       Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps);
   }
-  
+
   std::vector<MVT::ValueType> RetVals;
   MVT::ValueType RetTyVT = getValueType(RetTy);
   if (RetTyVT != MVT::isVoid)
     RetVals.push_back(RetTyVT);
   RetVals.push_back(MVT::Other);
 
-  SDOperand TheCall = SDOperand(DAG.getCall(RetVals, 
+  SDOperand TheCall = SDOperand(DAG.getCall(RetVals,
                                             Chain, Callee, args_to_use), 0);
   Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
   Chain = DAG.getNode(ISD::ADJCALLSTACKUP, MVT::Other, Chain,
@@ -462,7 +462,7 @@ LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
   }
   return std::make_pair(Result, Chain);
 }
-               
+
 
 std::pair<SDOperand, SDOperand> PPC32TargetLowering::
 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
@@ -484,7 +484,7 @@ class ISel : public SelectionDAGISel {
   SelectionDAG *ISelDAG;  // Hack to support us having a dag->dag transform
                           // for sdiv and udiv until it is put into the future
                           // dag combiner.
-  
+
   /// ExprMap - As shared expressions are codegen'd, we keep track of which
   /// vreg the value is produced in, so we only emit one copy of each compiled
   /// tree.
@@ -496,15 +496,15 @@ class ISel : public SelectionDAGISel {
 public:
   ISel(TargetMachine &TM) : SelectionDAGISel(PPC32Lowering), PPC32Lowering(TM),
                             ISelDAG(0) {}
-  
+
   /// runOnFunction - Override this function in order to reset our per-function
   /// variables.
   virtual bool runOnFunction(Function &Fn) {
     // Make sure we re-emit a set of the global base reg if necessary
     GlobalBaseInitialized = false;
     return SelectionDAGISel::runOnFunction(Fn);
-  } 
-  
+  }
+
   /// InstructionSelectBasicBlock - This callback is invoked by
   /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
   virtual void InstructionSelectBasicBlock(SelectionDAG &DAG) {
@@ -512,7 +512,7 @@ public:
     // Codegen the basic block.
     ISelDAG = &DAG;
     Select(DAG.getRoot());
-    
+
     // Clear state used for selection.
     ExprMap.clear();
     ISelDAG = 0;
@@ -521,7 +521,7 @@ public:
   // dag -> dag expanders for integer divide by constant
   SDOperand BuildSDIVSequence(SDOperand N);
   SDOperand BuildUDIVSequence(SDOperand N);
-  
+
   unsigned getGlobalBaseReg();
   unsigned getConstDouble(double floatVal, unsigned Result);
   void MoveCRtoGPR(unsigned CCReg, bool Inv, unsigned Idx, unsigned Result);
@@ -532,7 +532,7 @@ public:
   unsigned SelectExpr(SDOperand N, bool Recording=false);
   unsigned SelectExprFP(SDOperand N, unsigned Result);
   void Select(SDOperand N);
-  
+
   bool SelectAddr(SDOperand N, unsigned& Reg, int& offset);
   void SelectBranchCC(SDOperand N);
 };
@@ -555,7 +555,7 @@ static unsigned ExactLog2(unsigned Val) {
 // not, since all 1's are not contiguous.
 static bool IsRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
   bool isRun = true;
-  MB = 0; 
+  MB = 0;
   ME = 0;
 
   // look for first set bit
@@ -567,7 +567,7 @@ static bool IsRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
       break;
     }
   }
-  
+
   // look for last set bit
   for (; i < 32; i++) {
     if ((Val & (1 << (31 - i))) == 0)
@@ -580,7 +580,7 @@ static bool IsRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
     if ((Val & (1 << (31 - i))) != 0)
       break;
   }
-  
+
   // if we exhausted all the bits, we found a match at this point for 0*1*0*
   if (i == 32)
     return true;
@@ -596,7 +596,7 @@ static bool IsRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
     if ((Val & (1 << (31 - i))) == 0)
       break;
   }
-  
+
   // if we exhausted all the bits, then we found a match for 1*0*1*, otherwise,
   // the value is not a run of ones.
   if (i == 32)
@@ -620,7 +620,7 @@ static unsigned getImmediateForOpcode(SDOperand N, unsigned Opcode,
   if (N.getOpcode() != ISD::Constant) return 0;
 
   int v = (int)cast<ConstantSDNode>(N)->getSignExtended();
-  
+
   switch(Opcode) {
   default: return 0;
   case ISD::ADD:
@@ -666,7 +666,7 @@ static bool NodeHasRecordingVariant(unsigned NodeOpcode) {
   switch(NodeOpcode) {
   default: return false;
   case ISD::AND:
-  case ISD::OR: 
+  case ISD::OR:
     return true;
   }
 }
@@ -715,7 +715,7 @@ static unsigned getCROpForSetCC(unsigned Opcode, bool Inv1, bool Inv2) {
 static unsigned getCRIdxForSetCC(unsigned Condition, bool& Inv) {
   switch (Condition) {
   default: assert(0 && "Unknown condition!"); abort();
-  case ISD::SETULT: 
+  case ISD::SETULT:
   case ISD::SETLT:  Inv = false;  return 0;
   case ISD::SETUGE:
   case ISD::SETGE:  Inv = true;   return 0;
@@ -744,7 +744,7 @@ static unsigned IndexedOpForOp(unsigned Opcode) {
   return 0;
 }
 
-// Structure used to return the necessary information to codegen an SDIV as 
+// Structure used to return the necessary information to codegen an SDIV as
 // a multiply.
 struct ms {
   int m; // magic number
@@ -758,14 +758,14 @@ struct mu {
 };
 
 /// magic - calculate the magic numbers required to codegen an integer sdiv as
-/// a sequence of multiply and shifts.  Requires that the divisor not be 0, 1, 
+/// a sequence of multiply and shifts.  Requires that the divisor not be 0, 1,
 /// or -1.
 static struct ms magic(int d) {
   int p;
   unsigned int ad, anc, delta, q1, r1, q2, r2, t;
   const unsigned int two31 = 2147483648U; // 2^31
   struct ms mag;
-  
+
   ad = abs(d);
   t = two31 + ((unsigned int)d >> 31);
   anc = t - 1 - t%ad;   // absolute value of nc
@@ -847,7 +847,7 @@ SDOperand ISel::BuildSDIVSequence(SDOperand N) {
   int d = (int)cast<ConstantSDNode>(N.getOperand(1))->getSignExtended();
   ms magics = magic(d);
   // Multiply the numerator (operand 0) by the magic value
-  SDOperand Q = ISelDAG->getNode(ISD::MULHS, MVT::i32, N.getOperand(0), 
+  SDOperand Q = ISelDAG->getNode(ISD::MULHS, MVT::i32, N.getOperand(0),
                                  ISelDAG->getConstant(magics.m, MVT::i32));
   // If d > 0 and m < 0, add the numerator
   if (d > 0 && magics.m < 0)
@@ -857,10 +857,10 @@ SDOperand ISel::BuildSDIVSequence(SDOperand N) {
     Q = ISelDAG->getNode(ISD::SUB, MVT::i32, Q, N.getOperand(0));
   // Shift right algebraic if shift value is nonzero
   if (magics.s > 0)
-    Q = ISelDAG->getNode(ISD::SRA, MVT::i32, Q, 
+    Q = ISelDAG->getNode(ISD::SRA, MVT::i32, Q,
                          ISelDAG->getConstant(magics.s, MVT::i32));
   // Extract the sign bit and add it to the quotient
-  SDOperand T = 
+  SDOperand T =
     ISelDAG->getNode(ISD::SRL, MVT::i32, Q, ISelDAG->getConstant(31, MVT::i32));
   return ISelDAG->getNode(ISD::ADD, MVT::i32, Q, T);
 }
@@ -870,21 +870,21 @@ SDOperand ISel::BuildSDIVSequence(SDOperand N) {
 /// multiplying by a magic number.  See:
 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
 SDOperand ISel::BuildUDIVSequence(SDOperand N) {
-  unsigned d = 
+  unsigned d =
     (unsigned)cast<ConstantSDNode>(N.getOperand(1))->getSignExtended();
   mu magics = magicu(d);
   // Multiply the numerator (operand 0) by the magic value
-  SDOperand Q = ISelDAG->getNode(ISD::MULHU, MVT::i32, N.getOperand(0), 
+  SDOperand Q = ISelDAG->getNode(ISD::MULHU, MVT::i32, N.getOperand(0),
                                  ISelDAG->getConstant(magics.m, MVT::i32));
   if (magics.a == 0) {
-    Q = ISelDAG->getNode(ISD::SRL, MVT::i32, Q, 
+    Q = ISelDAG->getNode(ISD::SRL, MVT::i32, Q,
                          ISelDAG->getConstant(magics.s, MVT::i32));
   } else {
     SDOperand NPQ = ISelDAG->getNode(ISD::SUB, MVT::i32, N.getOperand(0), Q);
-    NPQ = ISelDAG->getNode(ISD::SRL, MVT::i32, NPQ, 
+    NPQ = ISelDAG->getNode(ISD::SRL, MVT::i32, NPQ,
                            ISelDAG->getConstant(1, MVT::i32));
     NPQ = ISelDAG->getNode(ISD::ADD, MVT::i32, NPQ, Q);
-    Q = ISelDAG->getNode(ISD::SRL, MVT::i32, NPQ, 
+    Q = ISelDAG->getNode(ISD::SRL, MVT::i32, NPQ,
                            ISelDAG->getConstant(magics.s-1, MVT::i32));
   }
   return Q;
@@ -906,7 +906,7 @@ unsigned ISel::getGlobalBaseReg() {
   return GlobalBaseReg;
 }
 
-/// getConstDouble - Loads a floating point value into a register, via the 
+/// getConstDouble - Loads a floating point value into a register, via the
 /// Constant Pool.  Optionally takes a register in which to load the value.
 unsigned ISel::getConstDouble(double doubleVal, unsigned Result=0) {
   unsigned Tmp1 = MakeReg(MVT::i32);
@@ -920,7 +920,7 @@ unsigned ISel::getConstDouble(double doubleVal, unsigned Result=0) {
   return Result;
 }
 
-/// MoveCRtoGPR - Move CCReg[Idx] to the least significant bit of Result.  If 
+/// MoveCRtoGPR - Move CCReg[Idx] to the least significant bit of Result.  If
 /// Inv is true, then invert the result.
 void ISel::MoveCRtoGPR(unsigned CCReg, bool Inv, unsigned Idx, unsigned Result){
   unsigned IntCR = MakeReg(MVT::i32);
@@ -937,7 +937,7 @@ void ISel::MoveCRtoGPR(unsigned CCReg, bool Inv, unsigned Idx, unsigned Result){
   }
 }
 
-/// SelectBitfieldInsert - turn an or of two masked values into 
+/// SelectBitfieldInsert - turn an or of two masked values into
 /// the rotate left word immediate then mask insert (rlwimi) instruction.
 /// Returns true on success, false if the caller still needs to select OR.
 ///
@@ -951,15 +951,15 @@ bool ISel::SelectBitfieldInsert(SDOperand OR, unsigned Result) {
   unsigned TgtMask = 0xFFFFFFFF, InsMask = 0xFFFFFFFF, Amount = 0;
   unsigned Op0Opc = OR.getOperand(0).getOpcode();
   unsigned Op1Opc = OR.getOperand(1).getOpcode();
-  
+
   // Verify that we have the correct opcodes
   if (ISD::SHL != Op0Opc && ISD::SRL != Op0Opc && ISD::AND != Op0Opc)
     return false;
   if (ISD::SHL != Op1Opc && ISD::SRL != Op1Opc && ISD::AND != Op1Opc)
     return false;
-    
+
   // Generate Mask value for Target
-  if (ConstantSDNode *CN = 
+  if (ConstantSDNode *CN =
       dyn_cast<ConstantSDNode>(OR.getOperand(0).getOperand(1).Val)) {
     switch(Op0Opc) {
     case ISD::SHL: TgtMask <<= (unsigned)CN->getValue(); break;
@@ -969,30 +969,30 @@ bool ISel::SelectBitfieldInsert(SDOperand OR, unsigned Result) {
   } else {
     return false;
   }
-  
+
   // Generate Mask value for Insert
-  if (ConstantSDNode *CN = 
+  if (ConstantSDNode *CN =
       dyn_cast<ConstantSDNode>(OR.getOperand(1).getOperand(1).Val)) {
     switch(Op1Opc) {
-    case ISD::SHL: 
-      Amount = CN->getValue(); 
+    case ISD::SHL:
+      Amount = CN->getValue();
       InsMask <<= Amount;
       if (Op0Opc == ISD::SRL) IsRotate = true;
       break;
-    case ISD::SRL: 
-      Amount = CN->getValue(); 
-      InsMask >>= Amount; 
+    case ISD::SRL:
+      Amount = CN->getValue();
+      InsMask >>= Amount;
       Amount = 32-Amount;
       if (Op0Opc == ISD::SHL) IsRotate = true;
       break;
-    case ISD::AND: 
+    case ISD::AND:
       InsMask &= (unsigned)CN->getValue();
       break;
     }
   } else {
     return false;
   }
-  
+
   // Verify that the Target mask and Insert mask together form a full word mask
   // and that the Insert mask is a run of set bits (which implies both are runs
   // of set bits).  Given that, Select the arguments and generate the rlwimi
@@ -1002,7 +1002,7 @@ bool ISel::SelectBitfieldInsert(SDOperand OR, unsigned Result) {
     unsigned Tmp1, Tmp2;
     // Check for rotlwi / rotrwi here, a special case of bitfield insert
     // where both bitfield halves are sourced from the same value.
-    if (IsRotate && 
+    if (IsRotate &&
         OR.getOperand(0).getOperand(0) == OR.getOperand(1).getOperand(0)) {
       Tmp1 = SelectExpr(OR.getOperand(0).getOperand(0));
       BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp1).addImm(Amount)
@@ -1039,12 +1039,12 @@ unsigned ISel::FoldIfWideZeroExtend(SDOperand N) {
 unsigned ISel::SelectCC(SDOperand CC, unsigned& Opc, bool &Inv, unsigned& Idx) {
   unsigned Result, Tmp1, Tmp2;
   bool AlreadySelected = false;
-  static const unsigned CompareOpcodes[] = 
+  static const unsigned CompareOpcodes[] =
     { PPC::FCMPU, PPC::FCMPU, PPC::CMPW, PPC::CMPLW };
-  
+
   // Allocate a condition register for this expression
   Result = RegMap->createVirtualRegister(PPC32::CRRCRegisterClass);
-  
+
   // If the first operand to the select is a SETCC node, then we can fold it
   // into the branch that selects which value to return.
   if (SetCCSDNode* SetCC = dyn_cast<SetCCSDNode>(CC.Val)) {
@@ -1054,12 +1054,12 @@ unsigned ISel::SelectCC(SDOperand CC, unsigned& Opc, bool &Inv, unsigned& Idx) {
 
     // Pass the optional argument U to getImmediateForOpcode for SETCC,
     // so that it knows whether the SETCC immediate range is signed or not.
-    if (1 == getImmediateForOpcode(SetCC->getOperand(1), ISD::SETCC, 
+    if (1 == getImmediateForOpcode(SetCC->getOperand(1), ISD::SETCC,
                                    Tmp2, U)) {
-      // For comparisons against zero, we can implicity set CR0 if a recording 
+      // For comparisons against zero, we can implicity set CR0 if a recording
       // variant (e.g. 'or.' instead of 'or') of the instruction that defines
       // operand zero of the SetCC node is available.
-      if (0 == Tmp2 && 
+      if (0 == Tmp2 &&
           NodeHasRecordingVariant(SetCC->getOperand(0).getOpcode()) &&
           SetCC->getOperand(0).Val->hasOneUse()) {
         RecordSuccess = false;
@@ -1098,7 +1098,7 @@ unsigned ISel::SelectCC(SDOperand CC, unsigned& Opc, bool &Inv, unsigned& Idx) {
   return Result;
 }
 
-unsigned ISel::SelectCCExpr(SDOperand N, unsigned& Opc, bool &Inv, 
+unsigned ISel::SelectCCExpr(SDOperand N, unsigned& Opc, bool &Inv,
                             unsigned &Idx) {
   bool Inv0, Inv1;
   unsigned Idx0, Idx1, CROpc, Opc1, Tmp1, Tmp2;
@@ -1148,7 +1148,7 @@ bool ISel::SelectAddr(SDOperand N, unsigned& Reg, int& offset)
     if (1 == getImmediateForOpcode(N.getOperand(1), opcode, imm)) {
       offset = imm;
       return false;
-    } 
+    }
     offset = SelectExpr(N.getOperand(1));
     return true;
   }
@@ -1159,14 +1159,14 @@ bool ISel::SelectAddr(SDOperand N, unsigned& Reg, int& offset)
 
 void ISel::SelectBranchCC(SDOperand N)
 {
-  MachineBasicBlock *Dest = 
+  MachineBasicBlock *Dest =
     cast<BasicBlockSDNode>(N.getOperand(2))->getBasicBlock();
 
   bool Inv;
   unsigned Opc, CCReg, Idx;
   Select(N.getOperand(0));  //chain
   CCReg = SelectCC(N.getOperand(1), Opc, Inv, Idx);
-  
+
   // Iterate to the next basic block, unless we're already at the end of the
   ilist<MachineBasicBlock>::iterator It = BB, E = BB->getParent()->end();
   if (++It == E) It = BB;
@@ -1176,7 +1176,7 @@ void ISel::SelectBranchCC(SDOperand N)
   // if necessary by the branch selection pass.  Otherwise, emit a standard
   // conditional branch.
   if (N.getOpcode() == ISD::BRCONDTWOWAY) {
-    MachineBasicBlock *Fallthrough = 
+    MachineBasicBlock *Fallthrough =
       cast<BasicBlockSDNode>(N.getOperand(3))->getBasicBlock();
     if (Dest != It) {
       BuildMI(BB, PPC::COND_BRANCH, 4).addReg(CCReg).addImm(Opc)
@@ -1221,7 +1221,7 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
       MVT::ValueType VT = SetCC->getOperand(0).getValueType();
       unsigned TV = SelectExpr(N.getOperand(1)); // Use if TRUE
       unsigned FV = SelectExpr(N.getOperand(2)); // Use if FALSE
-      
+
       ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(SetCC->getOperand(1));
       if (CN && (CN->isExactlyValue(-0.0) || CN->isExactlyValue(0.0))) {
         switch(SetCC->getCondition()) {
@@ -1282,13 +1282,13 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
       assert(0 && "Should never get here");
       return 0;
     }
-    
+
     bool Inv;
     unsigned TrueValue = SelectExpr(N.getOperand(1)); //Use if TRUE
     unsigned FalseValue = SelectExpr(N.getOperand(2)); //Use if FALSE
     unsigned CCReg = SelectCC(N.getOperand(0), Opc, Inv, Tmp3);
 
-    // Create an iterator with which to insert the MBB for copying the false 
+    // Create an iterator with which to insert the MBB for copying the false
     // value and the MBB to hold the PHI instruction for this SetCC.
     MachineBasicBlock *thisMBB = BB;
     const BasicBlock *LLVM_BB = BB->getBasicBlock();
@@ -1328,7 +1328,7 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
   }
 
   case ISD::FNEG:
-    if (!NoExcessFPPrecision && 
+    if (!NoExcessFPPrecision &&
         ISD::ADD == N.getOperand(0).getOpcode() &&
         N.getOperand(0).Val->hasOneUse() &&
         ISD::MUL == N.getOperand(0).getOperand(0).getOpcode() &&
@@ -1339,7 +1339,7 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
       Tmp3 = SelectExpr(N.getOperand(0).getOperand(1));
       Opc = DestType == MVT::f64 ? PPC::FNMADD : PPC::FNMADDS;
       BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
-    } else if (!NoExcessFPPrecision && 
+    } else if (!NoExcessFPPrecision &&
         ISD::ADD == N.getOperand(0).getOpcode() &&
         N.getOperand(0).Val->hasOneUse() &&
         ISD::MUL == N.getOperand(0).getOperand(1).getOpcode() &&
@@ -1358,23 +1358,23 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
       BuildMI(BB, PPC::FNEG, 1, Result).addReg(Tmp1);
     }
     return Result;
-    
+
   case ISD::FABS:
     Tmp1 = SelectExpr(N.getOperand(0));
     BuildMI(BB, PPC::FABS, 1, Result).addReg(Tmp1);
     return Result;
 
   case ISD::FP_ROUND:
-    assert (DestType == MVT::f32 && 
-            N.getOperand(0).getValueType() == MVT::f64 && 
+    assert (DestType == MVT::f32 &&
+            N.getOperand(0).getValueType() == MVT::f64 &&
             "only f64 to f32 conversion supported here");
     Tmp1 = SelectExpr(N.getOperand(0));
     BuildMI(BB, PPC::FRSP, 1, Result).addReg(Tmp1);
     return Result;
 
   case ISD::FP_EXTEND:
-    assert (DestType == MVT::f64 && 
-            N.getOperand(0).getValueType() == MVT::f32 && 
+    assert (DestType == MVT::f64 &&
+            N.getOperand(0).getValueType() == MVT::f32 &&
             "only f32 to f64 conversion supported here");
     Tmp1 = SelectExpr(N.getOperand(0));
     BuildMI(BB, PPC::FMR, 1, Result).addReg(Tmp1);
@@ -1386,13 +1386,13 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
     Tmp1 = dyn_cast<RegSDNode>(Node)->getReg();
     BuildMI(BB, PPC::FMR, 1, Result).addReg(Tmp1);
     return Result;
-    
+
   case ISD::ConstantFP: {
     ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
     Result = getConstDouble(CN->getValue(), Result);
     return Result;
   }
-    
+
   case ISD::ADD:
     if (!NoExcessFPPrecision && N.getOperand(0).getOpcode() == ISD::MUL &&
         N.getOperand(0).Val->hasOneUse()) {
@@ -1460,16 +1460,16 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
 
   case ISD::UINT_TO_FP:
   case ISD::SINT_TO_FP: {
-    assert (N.getOperand(0).getValueType() == MVT::i32 
+    assert (N.getOperand(0).getValueType() == MVT::i32
             && "int to float must operate on i32");
     bool IsUnsigned = (ISD::UINT_TO_FP == opcode);
     Tmp1 = SelectExpr(N.getOperand(0));  // Get the operand register
     Tmp2 = MakeReg(MVT::f64); // temp reg to load the integer value into
     Tmp3 = MakeReg(MVT::i32); // temp reg to hold the conversion constant
-    
+
     int FrameIdx = BB->getParent()->getFrameInfo()->CreateStackObject(8, 8);
     MachineConstantPool *CP = BB->getParent()->getConstantPool();
-    
+
     if (IsUnsigned) {
       unsigned ConstF = getConstDouble(0x1.000000p52);
       // Store the hi & low halves of the fp value, currently in int regs
@@ -1542,9 +1542,9 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
 
   if (ISD::CopyFromReg == opcode)
     DestType = N.getValue(0).getValueType();
-    
+
   if (DestType == MVT::f64 || DestType == MVT::f32)
-    if (ISD::LOAD != opcode && ISD::EXTLOAD != opcode && 
+    if (ISD::LOAD != opcode && ISD::EXTLOAD != opcode &&
         ISD::UNDEF != opcode && ISD::CALL != opcode)
       return SelectExprFP(N, Result);
 
@@ -1591,7 +1591,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
     Tmp1 = cast<FrameIndexSDNode>(N)->getIndex();
     addFrameReference(BuildMI(BB, PPC::ADDI, 2, Result), (int)Tmp1, 0, false);
     return Result;
-  
+
   case ISD::GlobalAddress: {
     GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
     Tmp1 = MakeReg(MVT::i32);
@@ -1612,7 +1612,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
     MVT::ValueType TypeBeingLoaded = (ISD::LOAD == opcode) ?
       Node->getValueType(0) : cast<MVTSDNode>(Node)->getExtraValueType();
     bool sext = (ISD::SEXTLOAD == opcode);
-    
+
     // Make sure we generate both values.
     if (Result != 1)
       ExprMap[N.getValue(1)] = 1;   // Generate the token
@@ -1632,7 +1632,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
     case MVT::f32: Opc = PPC::LFS; break;
     case MVT::f64: Opc = PPC::LFD; break;
     }
-    
+
     if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
       Tmp1 = MakeReg(MVT::i32);
       int CPI = CP->getIndex();
@@ -1655,10 +1655,10 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
     }
     return Result;
   }
-    
+
   case ISD::CALL: {
     unsigned GPR_idx = 0, FPR_idx = 0;
-    static const unsigned GPR[] = { 
+    static const unsigned GPR[] = {
       PPC::R3, PPC::R4, PPC::R5, PPC::R6,
       PPC::R7, PPC::R8, PPC::R9, PPC::R10,
     };
@@ -1673,13 +1673,13 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
 
     MachineInstr *CallMI;
     // Emit the correct call instruction based on the type of symbol called.
-    if (GlobalAddressSDNode *GASD = 
+    if (GlobalAddressSDNode *GASD =
         dyn_cast<GlobalAddressSDNode>(N.getOperand(1))) {
-      CallMI = BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(GASD->getGlobal(), 
+      CallMI = BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(GASD->getGlobal(),
                                                            true);
-    } else if (ExternalSymbolSDNode *ESSDN = 
+    } else if (ExternalSymbolSDNode *ESSDN =
                dyn_cast<ExternalSymbolSDNode>(N.getOperand(1))) {
-      CallMI = BuildMI(PPC::CALLpcrel, 1).addExternalSymbol(ESSDN->getSymbol(), 
+      CallMI = BuildMI(PPC::CALLpcrel, 1).addExternalSymbol(ESSDN->getSymbol(),
                                                             true);
     } else {
       Tmp1 = SelectExpr(N.getOperand(1));
@@ -1688,7 +1688,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
       CallMI = BuildMI(PPC::CALLindirect, 3).addImm(20).addImm(0)
         .addReg(PPC::R12);
     }
-       
+
     // Load the register args to virtual regs
     std::vector<unsigned> ArgVR;
     for(int i = 2, e = Node->getNumOperands(); i < e; ++i)
@@ -1718,7 +1718,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
         break;
       }
     }
-    
+
     // Put the call instruction in the correct place in the MachineBasicBlock
     BB->push_back(CallMI);
 
@@ -1750,17 +1750,17 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
     switch(cast<MVTSDNode>(Node)->getExtraValueType()) {
     default: Node->dump(); assert(0 && "Unhandled SIGN_EXTEND type"); break;
     case MVT::i16:
-      BuildMI(BB, PPC::EXTSH, 1, Result).addReg(Tmp1); 
+      BuildMI(BB, PPC::EXTSH, 1, Result).addReg(Tmp1);
       break;
     case MVT::i8:
-      BuildMI(BB, PPC::EXTSB, 1, Result).addReg(Tmp1); 
+      BuildMI(BB, PPC::EXTSB, 1, Result).addReg(Tmp1);
       break;
     case MVT::i1:
       BuildMI(BB, PPC::SUBFIC, 2, Result).addReg(Tmp1).addSImm(0);
       break;
     }
     return Result;
-    
+
   case ISD::CopyFromReg:
     if (Result == 1)
       Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
@@ -1779,7 +1779,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
       BuildMI(BB, PPC::SLW, 2, Result).addReg(Tmp1).addReg(Tmp2);
     }
     return Result;
-    
+
   case ISD::SRL:
     Tmp1 = SelectExpr(N.getOperand(0));
     if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
@@ -1791,7 +1791,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
       BuildMI(BB, PPC::SRW, 2, Result).addReg(Tmp1).addReg(Tmp2);
     }
     return Result;
-    
+
   case ISD::SRA:
     Tmp1 = SelectExpr(N.getOperand(0));
     if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
@@ -1802,7 +1802,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
       BuildMI(BB, PPC::SRAW, 2, Result).addReg(Tmp1).addReg(Tmp2);
     }
     return Result;
-  
+
   case ISD::ADD:
     assert (DestType == MVT::i32 && "Only do arithmetic on i32s!");
     Tmp1 = SelectExpr(N.getOperand(0));
@@ -1823,7 +1823,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
 
   case ISD::AND:
     if (PPCCRopts) {
-      if (N.getOperand(0).getOpcode() == ISD::SETCC || 
+      if (N.getOperand(0).getOpcode() == ISD::SETCC ||
           N.getOperand(1).getOpcode() == ISD::SETCC) {
         bool Inv;
         Tmp1 = SelectCCExpr(N, Opc, Inv, Tmp2);
@@ -1858,12 +1858,12 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
     }
     RecordSuccess = true;
     return Result;
-  
+
   case ISD::OR:
     if (SelectBitfieldInsert(N, Result))
       return Result;
     if (PPCCRopts) {
-      if (N.getOperand(0).getOpcode() == ISD::SETCC || 
+      if (N.getOperand(0).getOpcode() == ISD::SETCC ||
           N.getOperand(1).getOpcode() == ISD::SETCC) {
         bool Inv;
         Tmp1 = SelectCCExpr(N, Opc, Inv, Tmp2);
@@ -1951,7 +1951,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
       BuildMI(BB, PPC::SUBF, 2, Result).addReg(Tmp2).addReg(Tmp1);
     }
     return Result;
-    
+
   case ISD::MUL:
     Tmp1 = SelectExpr(N.getOperand(0));
     if (1 == getImmediateForOpcode(N.getOperand(1), opcode, Tmp2))
@@ -1992,7 +1992,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
     // constants to implement it as a multiply instead.
     case 4:
       ExprMap.erase(N);
-      if (opcode == ISD::SDIV) 
+      if (opcode == ISD::SDIV)
         return SelectExpr(BuildSDIVSequence(N));
       else
         return SelectExpr(BuildUDIVSequence(N));
@@ -2080,7 +2080,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
     }
     return Result+N.ResNo;
   }
-    
+
   case ISD::FP_TO_UINT:
   case ISD::FP_TO_SINT: {
     bool U = (ISD::FP_TO_UINT == opcode);
@@ -2151,10 +2151,10 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
     assert(0 && "Should never get here");
     return 0;
   }
- 
+
   case ISD::SETCC:
     if (SetCCSDNode *SetCC = dyn_cast<SetCCSDNode>(Node)) {
-      if (ConstantSDNode *CN = 
+      if (ConstantSDNode *CN =
           dyn_cast<ConstantSDNode>(SetCC->getOperand(1).Val)) {
         // We can codegen setcc op, imm very efficiently compared to a brcond.
         // Check for those cases here.
@@ -2226,7 +2226,7 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
           return Result;
         }
       }
-    
+
       bool Inv;
       unsigned CCReg = SelectCC(N, Opc, Inv, T