diff options
| author | Nate Begeman <natebegeman@mac.com> | 2005-07-20 22:42:00 +0000 |
|---|---|---|
| committer | Nate Begeman <natebegeman@mac.com> | 2005-07-20 22:42:00 +0000 |
| commit | adeb43ddf4eac9e75b7c8e79fa832f72922a2926 (patch) | |
| tree | a348bba538834e4ae4789b1cf3512fdfad43733f /lib/Target/PowerPC/PPCISelPattern.cpp | |
| parent | a57743780954ee455896f917d73af91f3430f0b1 (diff) | |
Generate mfocrf when targeting g5. Generate fsqrt/fsqrts when targetin g5.
8-byte align doubles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22486 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCISelPattern.cpp')
| -rw-r--r-- | lib/Target/PowerPC/PPCISelPattern.cpp | 21 |
1 files changed, 18 insertions, 3 deletions
diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp index 4365e39646..19ef823ad6 100644 --- a/lib/Target/PowerPC/PPCISelPattern.cpp +++ b/lib/Target/PowerPC/PPCISelPattern.cpp @@ -35,6 +35,11 @@ #include <algorithm> using namespace llvm; +// FIXME: temporary. +#include "llvm/Support/CommandLine.h" +static cl::opt<bool> EnableGPOPT("enable-gpopt", cl::Hidden, + cl::desc("Enable optimizations for GP cpus")); + //===----------------------------------------------------------------------===// // PPC32TargetLowering - PPC32 Implementation of the TargetLowering interface namespace { @@ -67,13 +72,17 @@ namespace { // We don't support sin/cos/sqrt/fmod setOperationAction(ISD::FSIN , MVT::f64, Expand); setOperationAction(ISD::FCOS , MVT::f64, Expand); - setOperationAction(ISD::FSQRT, MVT::f64, Expand); setOperationAction(ISD::SREM , MVT::f64, Expand); setOperationAction(ISD::FSIN , MVT::f32, Expand); setOperationAction(ISD::FCOS , MVT::f32, Expand); - setOperationAction(ISD::FSQRT, MVT::f32, Expand); setOperationAction(ISD::SREM , MVT::f32, Expand); + // If we're enabling GP optimizations, use hardware square root + if (!EnableGPOPT) { + setOperationAction(ISD::FSQRT, MVT::f64, Expand); + setOperationAction(ISD::FSQRT, MVT::f32, Expand); + } + //PowerPC does not have CTPOP or CTTZ setOperationAction(ISD::CTPOP, MVT::i32 , Expand); setOperationAction(ISD::CTTZ , MVT::i32 , Expand); @@ -961,7 +970,7 @@ unsigned ISel::getConstDouble(double doubleVal, unsigned Result=0) { void ISel::MoveCRtoGPR(unsigned CCReg, bool Inv, unsigned Idx, unsigned Result){ unsigned IntCR = MakeReg(MVT::i32); BuildMI(BB, PPC::MCRF, 1, PPC::CR7).addReg(CCReg); - BuildMI(BB, PPC::MFCR, 1, IntCR).addReg(PPC::CR7); + BuildMI(BB, EnableGPOPT ? PPC::MFOCRF : PPC::MFCR, 1, IntCR).addReg(PPC::CR7); if (Inv) { unsigned Tmp1 = MakeReg(MVT::i32); BuildMI(BB, PPC::RLWINM, 4, Tmp1).addReg(IntCR).addImm(32-(3-Idx)) @@ -2273,6 +2282,12 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) { BuildMI(BB, PPC::FABS, 1, Result).addReg(Tmp1); return Result; + case ISD::FSQRT: + Tmp1 = SelectExpr(N.getOperand(0)); + Opc = DestType == MVT::f64 ? PPC::FSQRT : PPC::FSQRTS; + BuildMI(BB, Opc, 1, Result).addReg(Tmp1); + return Result; + case ISD::FP_ROUND: assert (DestType == MVT::f32 && N.getOperand(0).getValueType() == MVT::f64 && |