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authorNate Begeman <natebegeman@mac.com>2005-04-06 06:44:57 +0000
committerNate Begeman <natebegeman@mac.com>2005-04-06 06:44:57 +0000
commit27b4c23b8085563158d1b6a4e8892fad999b579c (patch)
treee54177809111ed76b4f4d226e88f5691746205ec /lib/Target/PowerPC/PPCISelPattern.cpp
parentb70c2f3ef78cf3416991f8ee8c98c2d545b6d49d (diff)
Fixed version of optimized integer divide is now fixed. Calculate the
quotient, not the remainder. Also, make sure to remove the old div operand from the ExprMap and let SelectExpr insert the new one. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21111 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCISelPattern.cpp')
-rw-r--r--lib/Target/PowerPC/PPCISelPattern.cpp22
1 files changed, 9 insertions, 13 deletions
diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp
index 465a9bccf1..3ece1b29f9 100644
--- a/lib/Target/PowerPC/PPCISelPattern.cpp
+++ b/lib/Target/PowerPC/PPCISelPattern.cpp
@@ -551,7 +551,7 @@ static unsigned getImmediateForOpcode(SDOperand N, unsigned Opcode,
if (v <= -2 || v >= 2) { return 4; }
break;
case ISD::UDIV:
- if (v != 0) { return 4; }
+ if (v > 1) { return 4; }
break;
}
return 0;
@@ -711,10 +711,7 @@ SDOperand ISel::BuildSDIVSequence(SDOperand N) {
// Extract the sign bit and add it to the quotient
SDOperand T =
ISelDAG->getNode(ISD::SRL, MVT::i32, Q, ISelDAG->getConstant(31, MVT::i32));
- Q = ISelDAG->getNode(ISD::ADD, MVT::i32, Q, T);
- // Compute the remainder
- T = ISelDAG->getNode(ISD::MUL, MVT::i32, Q, N.getOperand(1));
- return ISelDAG->getNode(ISD::SUB, MVT::i32, N.getOperand(0), T);
+ return ISelDAG->getNode(ISD::ADD, MVT::i32, Q, T);
}
/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
@@ -739,9 +736,7 @@ SDOperand ISel::BuildUDIVSequence(SDOperand N) {
Q = ISelDAG->getNode(ISD::SRL, MVT::i32, NPQ,
ISelDAG->getConstant(magics.s-1, MVT::i32));
}
- // Compute the remainder
- SDOperand T = ISelDAG->getNode(ISD::MUL, MVT::i32, Q, N.getOperand(1));
- return ISelDAG->getNode(ISD::SUB, MVT::i32, N.getOperand(0), T);
+ return Q;
}
/// getGlobalBaseReg - Output the instructions required to put the
@@ -1601,11 +1596,12 @@ unsigned ISel::SelectExpr(SDOperand N) {
return Result;
// If this is a divide by constant, we can emit code using some magic
// constants to implement it as a multiply instead.
- //case 4:
- // if (opcode == ISD::SDIV)
- // return SelectExpr(BuildSDIVSequence(N));
- // else
- // return SelectExpr(BuildUDIVSequence(N));
+ case 4:
+ ExprMap.erase(N);
+ if (opcode == ISD::SDIV)
+ return SelectExpr(BuildSDIVSequence(N));
+ else
+ return SelectExpr(BuildUDIVSequence(N));
}
Tmp1 = SelectExpr(N.getOperand(0));
Tmp2 = SelectExpr(N.getOperand(1));