diff options
| author | Evan Cheng <evan.cheng@apple.com> | 2006-06-15 08:18:06 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2006-06-15 08:18:06 +0000 |
| commit | a7dc4a59cbb19cfb5dbc0f9ca500f26dddfbb7f6 (patch) | |
| tree | 6cdfa787b390608179b2b19d9a463bb90ece1ebe /lib/Target/PowerPC/PPCISelLowering.cpp | |
| parent | 015188ffbc148cb90184814fba51c4939c05a7e2 (diff) | |
Type of extract_element index operand should be iPTR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28797 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCISelLowering.cpp')
| -rw-r--r-- | lib/Target/PowerPC/PPCISelLowering.cpp | 27 |
1 files changed, 15 insertions, 12 deletions
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 03e0d38d10..a0142b165b 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -1334,7 +1334,8 @@ static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) { return FP; } -static SDOperand LowerSHL(SDOperand Op, SelectionDAG &DAG) { +static SDOperand LowerSHL(SDOperand Op, SelectionDAG &DAG, + MVT::ValueType PtrVT) { assert(Op.getValueType() == MVT::i64 && Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!"); // The generic code does a fine job expanding shift by a constant. @@ -1343,9 +1344,9 @@ static SDOperand LowerSHL(SDOperand Op, SelectionDAG &DAG) { // Otherwise, expand into a bunch of logical ops. Note that these ops // depend on the PPC behavior for oversized shift amounts. SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), - DAG.getConstant(0, MVT::i32)); + DAG.getConstant(0, PtrVT)); SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), - DAG.getConstant(1, MVT::i32)); + DAG.getConstant(1, PtrVT)); SDOperand Amt = Op.getOperand(1); SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, @@ -1361,7 +1362,8 @@ static SDOperand LowerSHL(SDOperand Op, SelectionDAG &DAG) { return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi); } -static SDOperand LowerSRL(SDOperand Op, SelectionDAG &DAG) { +static SDOperand LowerSRL(SDOperand Op, SelectionDAG &DAG, + MVT::ValueType PtrVT) { assert(Op.getValueType() == MVT::i64 && Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!"); // The generic code does a fine job expanding shift by a constant. @@ -1370,9 +1372,9 @@ static SDOperand LowerSRL(SDOperand Op, SelectionDAG &DAG) { // Otherwise, expand into a bunch of logical ops. Note that these ops // depend on the PPC behavior for oversized shift amounts. SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), - DAG.getConstant(0, MVT::i32)); + DAG.getConstant(0, PtrVT)); SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), - DAG.getConstant(1, MVT::i32)); + DAG.getConstant(1, PtrVT)); SDOperand Amt = Op.getOperand(1); SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, @@ -1388,7 +1390,8 @@ static SDOperand LowerSRL(SDOperand Op, SelectionDAG &DAG) { return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi); } -static SDOperand LowerSRA(SDOperand Op, SelectionDAG &DAG) { +static SDOperand LowerSRA(SDOperand Op, SelectionDAG &DAG, + MVT::ValueType PtrVT) { assert(Op.getValueType() == MVT::i64 && Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!"); // The generic code does a fine job expanding shift by a constant. @@ -1396,9 +1399,9 @@ static SDOperand LowerSRA(SDOperand Op, SelectionDAG &DAG) { // Otherwise, expand into a bunch of logical ops, followed by a select_cc. SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), - DAG.getConstant(0, MVT::i32)); + DAG.getConstant(0, PtrVT)); SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0), - DAG.getConstant(1, MVT::i32)); + DAG.getConstant(1, PtrVT)); SDOperand Amt = Op.getOperand(1); SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32, @@ -2132,9 +2135,9 @@ SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) { case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); // Lower 64-bit shifts. - case ISD::SHL: return LowerSHL(Op, DAG); - case ISD::SRL: return LowerSRL(Op, DAG); - case ISD::SRA: return LowerSRA(Op, DAG); + case ISD::SHL: return LowerSHL(Op, DAG, getPointerTy()); + case ISD::SRL: return LowerSRL(Op, DAG, getPointerTy()); + case ISD::SRA: return LowerSRA(Op, DAG, getPointerTy()); // Vector-related lowering. case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); |