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| author | Chris Lattner <sabre@nondot.org> | 2006-06-27 18:18:41 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2006-06-27 18:18:41 +0000 |
| commit | 563ecfbf8207ce941ddc0ee60c65378c6b9c572f (patch) | |
| tree | 8908c775c1f2b7c4d38a141986040cf20d2c4cfa /lib/Target/PowerPC/PPCISelLowering.cpp | |
| parent | e2f8ad854d6c07d89ddfa281c8459d4d7c3a5095 (diff) | |
Implement 64-bit undef, sub, shl/shr, srem/urem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28929 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCISelLowering.cpp')
| -rw-r--r-- | lib/Target/PowerPC/PPCISelLowering.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index a417a2d544..5122b5671b 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -58,6 +58,8 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM) // PowerPC has no SREM/UREM instructions setOperationAction(ISD::SREM, MVT::i32, Expand); setOperationAction(ISD::UREM, MVT::i32, Expand); + setOperationAction(ISD::SREM, MVT::i64, Expand); + setOperationAction(ISD::UREM, MVT::i64, Expand); // We don't support sin/cos/sqrt/fmod setOperationAction(ISD::FSIN , MVT::f64, Expand); |