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authorEvan Cheng <evan.cheng@apple.com>2008-03-08 00:58:38 +0000
committerEvan Cheng <evan.cheng@apple.com>2008-03-08 00:58:38 +0000
commit27b7db549e4c5bff4579d209304de5628513edeb (patch)
tree57198f184b01fe55ebbca8a70a05c679e1011b97 /lib/Target/PowerPC/PPCISelLowering.cpp
parenta2fcff4d97c8fecd58cd977c45f1a883bc6ae1c3 (diff)
Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} and prefetchnta instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48042 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCISelLowering.cpp')
-rw-r--r--lib/Target/PowerPC/PPCISelLowering.cpp1
1 files changed, 1 insertions, 0 deletions
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index 06098de063..15e3f2d0f2 100644
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -82,6 +82,7 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
setOperationAction(ISD::MEMSET, MVT::Other, Expand);
setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
+ setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
// PowerPC has no SREM/UREM instructions
setOperationAction(ISD::SREM, MVT::i32, Expand);