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| author | Dan Gohman <gohman@apple.com> | 2010-02-10 16:03:48 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2010-02-10 16:03:48 +0000 |
| commit | f451cb870efcf9e0302d25ed05f4cac6bb494e42 (patch) | |
| tree | f614bd15d6f3e0b944c58469b235dafc3e693747 /lib/Target/PowerPC/PPCISelDAGToDAG.cpp | |
| parent | c056baed8704bd715ee58e5dfe724c255e68abbd (diff) | |
Fix "the the" and similar typos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95781 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCISelDAGToDAG.cpp')
| -rw-r--r-- | lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index 32c1879cf7..004997fe8c 100644 --- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -199,7 +199,7 @@ void PPCDAGToDAGISel::InsertVRSaveCode(MachineFunction &Fn) { // Check to see if this function uses vector registers, which means we have to // save and restore the VRSAVE register and update it with the regs we use. // - // In this case, there will be virtual registers of vector type type created + // In this case, there will be virtual registers of vector type created // by the scheduler. Detect them now. bool HasVectorVReg = false; for (unsigned i = TargetRegisterInfo::FirstVirtualRegister, |