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authorHal Finkel <hfinkel@anl.gov>2013-03-26 18:57:22 +0000
committerHal Finkel <hfinkel@anl.gov>2013-03-26 18:57:22 +0000
commit01f99d29c3010f2891e5edb78182216214017063 (patch)
tree2bd58f29b57af06b316b5ee0661366f81a635855 /lib/Target/PowerPC/PPCFrameLowering.cpp
parent3b196f20fbd24b2c178a51e2473437655dc7066a (diff)
Use multiple virtual registers in PPC CR spilling
Now that the register scavenger can support multiple spill slots, and PEI can use virtual-register-based scavenging for multiple simultaneous registers, we can use a virtual register for the transfer register in the CR spilling code. This should eliminate the last place (outside of the prologue/epilogue) where we depend on the unconditional availability of the r0 register. We will soon be able to allocate it (in a somewhat restricted sense) as a GPR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178060 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCFrameLowering.cpp')
-rw-r--r--lib/Target/PowerPC/PPCFrameLowering.cpp7
1 files changed, 7 insertions, 0 deletions
diff --git a/lib/Target/PowerPC/PPCFrameLowering.cpp b/lib/Target/PowerPC/PPCFrameLowering.cpp
index f6c00f0d32..6a3951cf61 100644
--- a/lib/Target/PowerPC/PPCFrameLowering.cpp
+++ b/lib/Target/PowerPC/PPCFrameLowering.cpp
@@ -1094,6 +1094,13 @@ PPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF,
RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
RC->getAlignment(),
false));
+
+ // These kinds of spills might need two registers.
+ if (spillsCR(MF) || spillsVRSAVE(MF))
+ RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
+ RC->getAlignment(),
+ false));
+
}
}