diff options
| author | Nate Begeman <natebegeman@mac.com> | 2005-04-06 00:25:27 +0000 |
|---|---|---|
| committer | Nate Begeman <natebegeman@mac.com> | 2005-04-06 00:25:27 +0000 |
| commit | 815d6dac1ecc6ad661cebb308f9c06583fcd3cf0 (patch) | |
| tree | 16a1d8f9c6cf3d3983f6292b833f5689a2f663a8 /lib/Target/PowerPC/PPC64ISelPattern.cpp | |
| parent | c105e19864f2792c52bc6bb765d365308f38f461 (diff) | |
Add support for MULHS and MULHU nodes
Have LegalizeDAG handle SREM and UREM for us
Codegen SDIV and UDIV by constant as a multiply by magic constant instead
of integer divide, which is very slow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21104 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPC64ISelPattern.cpp')
| -rw-r--r-- | lib/Target/PowerPC/PPC64ISelPattern.cpp | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/lib/Target/PowerPC/PPC64ISelPattern.cpp b/lib/Target/PowerPC/PPC64ISelPattern.cpp index 5f5ba5c0ce..cbff20f866 100644 --- a/lib/Target/PowerPC/PPC64ISelPattern.cpp +++ b/lib/Target/PowerPC/PPC64ISelPattern.cpp @@ -1069,7 +1069,6 @@ unsigned ISel::SelectExpr(SDOperand N) { MVT::ValueType TypeBeingLoaded = (ISD::LOAD == opcode) ? Node->getValueType(0) : cast<MVTSDNode>(Node)->getExtraValueType(); bool sext = (ISD::SEXTLOAD == opcode); - bool byte = (MVT::i8 == TypeBeingLoaded); // Make sure we generate both values. if (Result != 1) |