diff options
| author | Misha Brukman <brukman+llvm@gmail.com> | 2004-08-17 04:55:41 +0000 |
|---|---|---|
| committer | Misha Brukman <brukman+llvm@gmail.com> | 2004-08-17 04:55:41 +0000 |
| commit | f2ccb77ee9d8ab35866dae111fa36929689c7511 (patch) | |
| tree | c1b71d510e6af6c32a71dd944bc85b6f468327b9 /lib/Target/PowerPC/PPC32ISelSimple.cpp | |
| parent | 2c38413b3f5420f45f2f8220b21862246d446dd0 (diff) | |
PowerPC 32-/64-bit split: Part I, PPC32* bit files, adapted from former PowerPC*
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15850 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPC32ISelSimple.cpp')
| -rw-r--r-- | lib/Target/PowerPC/PPC32ISelSimple.cpp | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/lib/Target/PowerPC/PPC32ISelSimple.cpp b/lib/Target/PowerPC/PPC32ISelSimple.cpp index b1251d5d78..50fd87b142 100644 --- a/lib/Target/PowerPC/PPC32ISelSimple.cpp +++ b/lib/Target/PowerPC/PPC32ISelSimple.cpp @@ -1,4 +1,4 @@ -//===-- InstSelectSimple.cpp - A simple instruction selector for PowerPC --===// +//===-- PPC32ISelSimple.cpp - A simple instruction selector PowerPC32 -----===// // // The LLVM Compiler Infrastructure // @@ -98,7 +98,7 @@ namespace { unsigned GlobalBaseReg; bool GlobalBaseInitialized; - ISel(TargetMachine &tm) : TM(reinterpret_cast<PPC32TargetMachine&>(tm)), + ISel(TargetMachine &tm) : TM(reinterpret_cast<PPC32TargetMachine&>(tm)), F(0), BB(0) {} bool doInitialization(Module &M) { @@ -381,10 +381,10 @@ namespace { /// high 32 bits of the long value, and the regNum+1 is the low 32 bits. /// unsigned makeAnotherReg(const Type *Ty) { - assert(dynamic_cast<const PowerPCRegisterInfo*>(TM.getRegisterInfo()) && + assert(dynamic_cast<const PPC32RegisterInfo*>(TM.getRegisterInfo()) && "Current target doesn't have PPC reg info??"); - const PowerPCRegisterInfo *PPCRI = - static_cast<const PowerPCRegisterInfo*>(TM.getRegisterInfo()); + const PPC32RegisterInfo *PPCRI = + static_cast<const PPC32RegisterInfo*>(TM.getRegisterInfo()); if (Ty == Type::LongTy || Ty == Type::ULongTy) { const TargetRegisterClass *RC = PPCRI->getRegClassForType(Type::IntTy); // Create the upper part @@ -1403,7 +1403,7 @@ void ISel::visitBranchInst(BranchInst &BI) { } else { // Change to the inverse condition... if (BI.getSuccessor(1) != NextBB) { - Opcode = PowerPCInstrInfo::invertPPCBranchOpcode(Opcode); + Opcode = PPC32InstrInfo::invertPPCBranchOpcode(Opcode); BuildMI(BB, PPC::COND_BRANCH, 3).addReg(PPC::CR0).addImm(Opcode) .addMBB(MBBMap[BI.getSuccessor(1)]) .addMBB(MBBMap[BI.getSuccessor(0)]); |