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| author | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2012-11-13 18:40:58 +0000 |
|---|---|---|
| committer | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2012-11-13 18:40:58 +0000 |
| commit | b64e2115de3b293ef706b75f040277477c949208 (patch) | |
| tree | 02290b789956eaf291cce86fad38cc7c22df9aa5 /lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp | |
| parent | 206252cc9f5509b27aa0761c677fdee8daff001c (diff) | |
Do not consider a machine instruction that uses and defines the same
physical register as candidate for common subexpression elimination
in MachineCSE.
This fixes a bug on PowerPC in MultiSource/Applications/oggenc/oggenc
caused by MachineCSE invalidly merging two separate DYNALLOC insns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167855 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp')
0 files changed, 0 insertions, 0 deletions