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| author | Jyotsna Verma <jverma@codeaurora.org> | 2013-03-05 18:42:28 +0000 |
|---|---|---|
| committer | Jyotsna Verma <jverma@codeaurora.org> | 2013-03-05 18:42:28 +0000 |
| commit | ee0ef13eba037055d8dc315fc924d967c8f8ce0a (patch) | |
| tree | 886e7aa9b4bc9ddf16917fda1fa75d1b9c5b3b42 /lib/Target/Mips/MipsMachineFunction.cpp | |
| parent | 62f38ca141f87ff3ed9334fbe6a5e1c45d40ca86 (diff) | |
Hexagon: Add encoding bits to the TFR64 instructions.
Set imMoveImm, isAsCheapAsAMove flags for TFRI instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176499 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsMachineFunction.cpp')
0 files changed, 0 insertions, 0 deletions