diff options
| author | Chris Lattner <sabre@nondot.org> | 2008-01-07 07:27:27 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2008-01-07 07:27:27 +0000 |
| commit | 749c6f6b5ed301c84aac562e414486549d7b98eb (patch) | |
| tree | 275f34b73cd0673d5e8fdcfe02cdb6d60c5422c2 /lib/Target/Mips/MipsInstrInfo.cpp | |
| parent | 682b8aed0779ac0c9a6a13d79ccc1cff3e9730cf (diff) | |
rename TargetInstrDescriptor -> TargetInstrDesc.
Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45695 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsInstrInfo.cpp')
| -rw-r--r-- | lib/Target/Mips/MipsInstrInfo.cpp | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/lib/Target/Mips/MipsInstrInfo.cpp b/lib/Target/Mips/MipsInstrInfo.cpp index 8896b35aed..85c1048d34 100644 --- a/lib/Target/Mips/MipsInstrInfo.cpp +++ b/lib/Target/Mips/MipsInstrInfo.cpp @@ -175,7 +175,7 @@ bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, // If there is only one terminator instruction, process it. unsigned LastOpc = LastInst->getOpcode(); if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) { - if (!LastInst->getDesc()->isBranch()) + if (!LastInst->getDesc().isBranch()) return true; // Unconditional branch @@ -259,7 +259,7 @@ InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, } else { // Conditional branch. unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm()); - const TargetInstrDescriptor &TID = get(Opc); + const TargetInstrDesc &TID = get(Opc); if (TID.getNumOperands() == 3) BuildMI(&MBB, TID).addReg(Cond[1].getReg()) @@ -275,15 +275,13 @@ InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, // Two-way Conditional branch. unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm()); - const TargetInstrDescriptor &TID = get(Opc); + const TargetInstrDesc &TID = get(Opc); if (TID.getNumOperands() == 3) - BuildMI(&MBB, TID).addReg(Cond[1].getReg()) - .addReg(Cond[2].getReg()) + BuildMI(&MBB, TID).addReg(Cond[1].getReg()).addReg(Cond[2].getReg()) .addMBB(TBB); else - BuildMI(&MBB, TID).addReg(Cond[1].getReg()) - .addMBB(TBB); + BuildMI(&MBB, TID).addReg(Cond[1].getReg()).addMBB(TBB); BuildMI(&MBB, get(Mips::J)).addMBB(FBB); return 2; |