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authorOwen Anderson <resistor@mac.com>2008-01-07 01:35:02 +0000
committerOwen Anderson <resistor@mac.com>2008-01-07 01:35:02 +0000
commit43dbe05279b753aabda571d9c83eaeb36987001a (patch)
treeb767b17e91b91d3bb7f897f507175fd60ebadb6b /lib/Target/Mips/MipsInstrInfo.cpp
parent93f96d00bf10299246ea726956ce84dcb4b9a59e (diff)
Move even more functionality from MRegisterInfo into TargetInstrInfo.
Some day I'll get it all moved over... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45672 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Mips/MipsInstrInfo.cpp')
-rw-r--r--lib/Target/Mips/MipsInstrInfo.cpp31
1 files changed, 31 insertions, 0 deletions
diff --git a/lib/Target/Mips/MipsInstrInfo.cpp b/lib/Target/Mips/MipsInstrInfo.cpp
index 30d680522d..130bfb8ed5 100644
--- a/lib/Target/Mips/MipsInstrInfo.cpp
+++ b/lib/Target/Mips/MipsInstrInfo.cpp
@@ -371,6 +371,37 @@ void MipsInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
return;
}
+MachineInstr *MipsInstrInfo::
+foldMemoryOperand(MachineInstr* MI,
+ SmallVectorImpl<unsigned> &Ops, int FI) const
+{
+ if (Ops.size() != 1) return NULL;
+
+ MachineInstr *NewMI = NULL;
+
+ switch (MI->getOpcode())
+ {
+ case Mips::ADDu:
+ if ((MI->getOperand(0).isRegister()) &&
+ (MI->getOperand(1).isRegister()) &&
+ (MI->getOperand(1).getReg() == Mips::ZERO) &&
+ (MI->getOperand(2).isRegister()))
+ {
+ if (Ops[0] == 0) // COPY -> STORE
+ NewMI = BuildMI(get(Mips::SW)).addFrameIndex(FI)
+ .addImm(0).addReg(MI->getOperand(2).getReg());
+ else // COPY -> LOAD
+ NewMI = BuildMI(get(Mips::LW), MI->getOperand(0)
+ .getReg()).addImm(0).addFrameIndex(FI);
+ }
+ break;
+ }
+
+ if (NewMI)
+ NewMI->copyKillDeadInfo(MI);
+ return NewMI;
+}
+
unsigned MipsInstrInfo::
RemoveBranch(MachineBasicBlock &MBB) const
{