diff options
| author | Anton Korobeynikov <asl@math.spbu.ru> | 2009-05-03 13:05:22 +0000 |
|---|---|---|
| committer | Anton Korobeynikov <asl@math.spbu.ru> | 2009-05-03 13:05:22 +0000 |
| commit | cf9adf2cbb8298e83b53d7bee2ddab4c875cb3c5 (patch) | |
| tree | 3852b9a4c9d29baabe21e52e43e9149bc3ab0eab /lib/Target/MSP430/MSP430CallingConv.td | |
| parent | 0fc32dae8f380f57087bf48e4248f1ad3326a1b0 (diff) | |
Add 8-bit regclass and pattern for sext_inreg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70721 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/MSP430/MSP430CallingConv.td')
| -rw-r--r-- | lib/Target/MSP430/MSP430CallingConv.td | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/MSP430/MSP430CallingConv.td b/lib/Target/MSP430/MSP430CallingConv.td index e60a3de13f..e582698227 100644 --- a/lib/Target/MSP430/MSP430CallingConv.td +++ b/lib/Target/MSP430/MSP430CallingConv.td @@ -14,7 +14,7 @@ //===----------------------------------------------------------------------===// def RetCC_MSP430 : CallingConv<[ // i16 are returned in registers R15, R14, R13, R12 - CCIfType<[i16], CCAssignToReg<[R15, R14, R13, R12]>> + CCIfType<[i16], CCAssignToReg<[R15W, R14W, R13W, R12W]>> ]>; //===----------------------------------------------------------------------===// @@ -26,7 +26,7 @@ def CC_MSP430 : CallingConv<[ // The first 4 integer arguments of non-varargs functions are passed in // integer registers. - CCIfNotVarArg<CCIfType<[i16], CCAssignToReg<[R15, R14, R13, R12]>>>, + CCIfNotVarArg<CCIfType<[i16], CCAssignToReg<[R15W, R14W, R13W, R12W]>>>, // Integer values get stored in stack slots that are 2 bytes in // size and 2-byte aligned. |