diff options
| author | Scott Michel <scottm@aero.org> | 2007-12-19 07:35:06 +0000 |
|---|---|---|
| committer | Scott Michel <scottm@aero.org> | 2007-12-19 07:35:06 +0000 |
| commit | 9999e685ea86e9cb8c8d59bfb2f3f4c20acc4de4 (patch) | |
| tree | 64fdb28243554d91576855e5370eb6ecf61c5f3a /lib/Target/CellSPU/SPUInstrInfo.cpp | |
| parent | 83870769c60b878fe03c04b853164b7404fa506f (diff) | |
Add new immed16.ll test case, fix CellSPU errata to make test case work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45196 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/CellSPU/SPUInstrInfo.cpp')
| -rw-r--r-- | lib/Target/CellSPU/SPUInstrInfo.cpp | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/lib/Target/CellSPU/SPUInstrInfo.cpp b/lib/Target/CellSPU/SPUInstrInfo.cpp index 5846aad72e..efd45f56dc 100644 --- a/lib/Target/CellSPU/SPUInstrInfo.cpp +++ b/lib/Target/CellSPU/SPUInstrInfo.cpp @@ -62,7 +62,6 @@ SPUInstrInfo::isMoveInstr(const MachineInstr& MI, case SPU::AHIvec: case SPU::AHIr16: case SPU::AIvec: - case SPU::AIr32: assert(MI.getNumOperands() == 3 && MI.getOperand(0).isRegister() && MI.getOperand(1).isRegister() && @@ -74,6 +73,19 @@ SPUInstrInfo::isMoveInstr(const MachineInstr& MI, return true; } break; + case SPU::AIr32: + assert(MI.getNumOperands() == 3 && + "wrong number of operands to AIr32"); + if (MI.getOperand(0).isRegister() && + (MI.getOperand(1).isRegister() || + MI.getOperand(1).isFrameIndex()) && + (MI.getOperand(2).isImmediate() && + MI.getOperand(2).getImmedValue() == 0)) { + sourceReg = MI.getOperand(1).getReg(); + destReg = MI.getOperand(0).getReg(); + return true; + } + break; #if 0 case SPU::ORIf64: case SPU::ORIf32: |