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| author | Evan Cheng <evan.cheng@apple.com> | 2008-09-24 00:05:32 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2008-09-24 00:05:32 +0000 |
| commit | da43bcf624acb56a3d77bb5ae9a02728af032613 (patch) | |
| tree | dd93cba15bfa2de5c6708211ff7d67d79792c3d6 /lib/Target/CellSPU/SPUISelLowering.cpp | |
| parent | dd4924c564c7a661b78b604ebf16dfef7aa62b35 (diff) | |
Properly handle 'm' inline asm constraints. If a GV is being selected for the addressing mode, it requires the same logic for PIC relative addressing, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56526 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/CellSPU/SPUISelLowering.cpp')
| -rw-r--r-- | lib/Target/CellSPU/SPUISelLowering.cpp | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp index ab64aae926..285c5b6f1e 100644 --- a/lib/Target/CellSPU/SPUISelLowering.cpp +++ b/lib/Target/CellSPU/SPUISelLowering.cpp @@ -3040,10 +3040,12 @@ SPUTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, void SPUTargetLowering::LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter, + bool hasMemory, std::vector<SDValue> &Ops, SelectionDAG &DAG) const { // Default, for the time being, to the base class handler - TargetLowering::LowerAsmOperandForConstraint(Op, ConstraintLetter, Ops, DAG); + TargetLowering::LowerAsmOperandForConstraint(Op, ConstraintLetter, hasMemory, + Ops, DAG); } /// isLegalAddressImmediate - Return true if the integer value can be used |