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| author | Evan Cheng <evan.cheng@apple.com> | 2010-09-28 23:50:49 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2010-09-28 23:50:49 +0000 |
| commit | 63d66eed16a6ee4e838f2f7a4c8299def0722c20 (patch) | |
| tree | 8f6d45aaa9b70a0694825dabb532e81b91a6622d /lib/Target/Alpha | |
| parent | e48155b25a40e0c1f285ab42b99b2503638d6c0d (diff) | |
Add support to model pipeline bypass / forwarding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115005 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha')
| -rw-r--r-- | lib/Target/Alpha/AlphaSchedule.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/Alpha/AlphaSchedule.td b/lib/Target/Alpha/AlphaSchedule.td index 3723a07e87..3703dd4fa9 100644 --- a/lib/Target/Alpha/AlphaSchedule.td +++ b/lib/Target/Alpha/AlphaSchedule.td @@ -54,7 +54,7 @@ def s_pseudo : InstrItinClass; //modified some def Alpha21264Itineraries : ProcessorItineraries< - [L0, L1, FST0, FST1, U0, U1, FA, FM], [ + [L0, L1, FST0, FST1, U0, U1, FA, FM], [], [ InstrItinData<s_ild , [InstrStage<3, [L0, L1]>]>, InstrItinData<s_fld , [InstrStage<4, [L0, L1]>]>, InstrItinData<s_ist , [InstrStage<0, [L0, L1]>]>, |