diff options
author | Andrew Lenharth <andrewl@lenharth.org> | 2005-03-02 17:21:38 +0000 |
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committer | Andrew Lenharth <andrewl@lenharth.org> | 2005-03-02 17:21:38 +0000 |
commit | e4f161c909a8ee35efd6e9f02fc3d32a756a6268 (patch) | |
tree | e97aabdea262b25ca98f3ba7d64816e9dc558e7e /lib/Target/Alpha/AlphaTargetMachine.cpp | |
parent | 0c7490617a62b0622d52949c0651da907b3d6c04 (diff) |
Added LSR as a beta pass for alpha
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20407 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha/AlphaTargetMachine.cpp')
-rw-r--r-- | lib/Target/Alpha/AlphaTargetMachine.cpp | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/lib/Target/Alpha/AlphaTargetMachine.cpp b/lib/Target/Alpha/AlphaTargetMachine.cpp index b077f07448..80a88662a1 100644 --- a/lib/Target/Alpha/AlphaTargetMachine.cpp +++ b/lib/Target/Alpha/AlphaTargetMachine.cpp @@ -26,6 +26,12 @@ namespace { RegisterTarget<AlphaTargetMachine> X("alpha", " Alpha (incomplete)"); } +namespace llvm { + cl::opt<bool> EnableAlphaLSR("enable-lsr-for-alpha", + cl::desc("Enable LSR for Alpha (beta option!)"), + cl::Hidden); +} + unsigned AlphaTargetMachine::getModuleMatchQuality(const Module &M) { // We strongly match "alpha*". std::string TT = M.getTargetTriple(); @@ -54,6 +60,9 @@ AlphaTargetMachine::AlphaTargetMachine( const Module &M, IntrinsicLowering *IL) bool AlphaTargetMachine::addPassesToEmitAssembly(PassManager &PM, std::ostream &Out) { + if (EnableAlphaLSR) + PM.add(createLoopStrengthReducePass()); + // FIXME: Implement efficient support for garbage collection intrinsics. PM.add(createLowerGCPass()); |