diff options
| author | Evan Cheng <evan.cheng@apple.com> | 2007-12-05 03:14:33 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2007-12-05 03:14:33 +0000 |
| commit | d64b5c82b97ad1b74eb9fd2f23257a7899b0c307 (patch) | |
| tree | 833ba21d24aa346a057bf617a4b89ce36d9ae304 /lib/Target/Alpha/AlphaRegisterInfo.cpp | |
| parent | f89a22a3d1d98b8507433acf0cec7640e6da0088 (diff) | |
Add a argument to storeRegToStackSlot and storeRegToAddr to specify whether
the stored register is killed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44600 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha/AlphaRegisterInfo.cpp')
| -rw-r--r-- | lib/Target/Alpha/AlphaRegisterInfo.cpp | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp index b8e2c26827..8185a796f7 100644 --- a/lib/Target/Alpha/AlphaRegisterInfo.cpp +++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp @@ -61,28 +61,29 @@ AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii) void AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, - unsigned SrcReg, int FrameIdx, - const TargetRegisterClass *RC) const { + unsigned SrcReg, bool isKill, int FrameIdx, + const TargetRegisterClass *RC) const { //cerr << "Trying to store " << getPrettyName(SrcReg) << " to " // << FrameIdx << "\n"; //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg); if (RC == Alpha::F4RCRegisterClass) BuildMI(MBB, MI, TII.get(Alpha::STS)) - .addReg(SrcReg, false, false, true) + .addReg(SrcReg, false, false, isKill) .addFrameIndex(FrameIdx).addReg(Alpha::F31); else if (RC == Alpha::F8RCRegisterClass) BuildMI(MBB, MI, TII.get(Alpha::STT)) - .addReg(SrcReg, false, false, true) + .addReg(SrcReg, false, false, isKill) .addFrameIndex(FrameIdx).addReg(Alpha::F31); else if (RC == Alpha::GPRCRegisterClass) BuildMI(MBB, MI, TII.get(Alpha::STQ)) - .addReg(SrcReg, false, false, true) + .addReg(SrcReg, false, false, isKill) .addFrameIndex(FrameIdx).addReg(Alpha::F31); else abort(); } void AlphaRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, + bool isKill, SmallVectorImpl<MachineOperand> &Addr, const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const { @@ -96,7 +97,7 @@ void AlphaRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, else abort(); MachineInstrBuilder MIB = - BuildMI(TII.get(Opc)).addReg(SrcReg, false, false, true); + BuildMI(TII.get(Opc)).addReg(SrcReg, false, false, isKill); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; if (MO.isRegister()) |