diff options
| author | Chris Lattner <sabre@nondot.org> | 2005-09-30 01:29:42 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2005-09-30 01:29:42 +0000 |
| commit | 97d5e6461a28790fa341d9e3b58f043db549dc6a (patch) | |
| tree | 00293d7848486e66ce181981b28822b890fc744a /lib/Target/Alpha/AlphaRegisterInfo.cpp | |
| parent | bf9716b9c48d3b0370c715cd79540945f73dc296 (diff) | |
Pass extra regclasses into spilling code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23537 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha/AlphaRegisterInfo.cpp')
| -rw-r--r-- | lib/Target/Alpha/AlphaRegisterInfo.cpp | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp index b6c93531c9..ac7d3f146f 100644 --- a/lib/Target/Alpha/AlphaRegisterInfo.cpp +++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp @@ -75,7 +75,8 @@ static const TargetRegisterClass *getClass(unsigned SrcReg) { void AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, - unsigned SrcReg, int FrameIdx) const { + unsigned SrcReg, int FrameIdx, + const TargetRegisterClass *RC) const { //std::cerr << "Trying to store " << getPrettyName(SrcReg) << " to " << FrameIdx << "\n"; //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg); if (EnableAlphaLSMark) @@ -92,7 +93,8 @@ AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, void AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, - unsigned DestReg, int FrameIdx) const{ + unsigned DestReg, int FrameIdx, + const TargetRegisterClass *RC) const { //std::cerr << "Trying to load " << getPrettyName(DestReg) << " to " << FrameIdx << "\n"; if (EnableAlphaLSMark) BuildMI(MBB, MI, Alpha::MEMLABEL, 4).addImm(4).addImm(0).addImm(2) |