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| author | Andrew Lenharth <andrewl@lenharth.org> | 2005-03-13 00:43:20 +0000 |
|---|---|---|
| committer | Andrew Lenharth <andrewl@lenharth.org> | 2005-03-13 00:43:20 +0000 |
| commit | 84e2dc2d5dab78e1db73b33bf4bc1878b47744fa (patch) | |
| tree | a36a998627edface39479c832a7b95fd4855185f /lib/Target/Alpha/AlphaRegisterInfo.cpp | |
| parent | a4319e58265e2113e3783a6d0b83e1d9a9721b81 (diff) | |
Should fix mesa
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20577 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha/AlphaRegisterInfo.cpp')
| -rw-r--r-- | lib/Target/Alpha/AlphaRegisterInfo.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp index 7a4df2bd35..3c8c616f00 100644 --- a/lib/Target/Alpha/AlphaRegisterInfo.cpp +++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp @@ -196,7 +196,7 @@ AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { //insert the new MachineInstr* nMI=BuildMI(Alpha::LDAH, 2, Alpha::R28) .addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30); - MBB.insert(--II, nMI); + MBB.insert(II, nMI); } else { MI.SetMachineOperandConst(i, MachineOperand::MO_SignExtendedImmed, Offset); } |