diff options
| author | Evan Cheng <evan.cheng@apple.com> | 2007-10-05 01:32:41 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2007-10-05 01:32:41 +0000 |
| commit | 66f0f640820b61cf9db814b6d187bae9faf7279c (patch) | |
| tree | 4d3b6ebbdf3bc1e7a4c69c6aa7d4a64931ff8820 /lib/Target/Alpha/AlphaRegisterInfo.cpp | |
| parent | 39305cf55363046162c5a992f96f26d607a204e5 (diff) | |
- Added a few target hooks to generate load / store instructions from / to any
address (not just from / to frameindexes).
- Added target hooks to unfold load / store instructions / SDNodes into separate
load, data processing, store instructions / SDNodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42621 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha/AlphaRegisterInfo.cpp')
| -rw-r--r-- | lib/Target/Alpha/AlphaRegisterInfo.cpp | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp index 08c4c94c03..7959483cb5 100644 --- a/lib/Target/Alpha/AlphaRegisterInfo.cpp +++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp @@ -82,6 +82,31 @@ AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, abort(); } +void AlphaRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, + SmallVector<MachineOperand,4> Addr, + const TargetRegisterClass *RC, + SmallVector<MachineInstr*, 4> &NewMIs) const { + unsigned Opc = 0; + if (RC == Alpha::F4RCRegisterClass) + Opc = Alpha::STS; + else if (RC == Alpha::F8RCRegisterClass) + Opc = Alpha::STT; + else if (RC == Alpha::GPRCRegisterClass) + Opc = Alpha::STQ; + else + abort(); + MachineInstrBuilder MIB = + BuildMI(TII.get(Opc)).addReg(SrcReg, false, false, true); + for (unsigned i = 0, e = Addr.size(); i != e; ++i) { + MachineOperand &MO = Addr[i]; + if (MO.isRegister()) + MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit()); + else + MIB.addImm(MO.getImm()); + } + NewMIs.push_back(MIB); +} + void AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, @@ -102,6 +127,31 @@ AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, abort(); } +void AlphaRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, + SmallVector<MachineOperand,4> Addr, + const TargetRegisterClass *RC, + SmallVector<MachineInstr*, 4> &NewMIs) const { + unsigned Opc = 0; + if (RC == Alpha::F4RCRegisterClass) + Opc = Alpha::LDS; + else if (RC == Alpha::F8RCRegisterClass) + Opc = Alpha::LDT; + else if (RC == Alpha::GPRCRegisterClass) + Opc = Alpha::LDQ; + else + abort(); + MachineInstrBuilder MIB = + BuildMI(TII.get(Opc), DestReg); + for (unsigned i = 0, e = Addr.size(); i != e; ++i) { + MachineOperand &MO = Addr[i]; + if (MO.isRegister()) + MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit()); + else + MIB.addImm(MO.getImm()); + } + NewMIs.push_back(MIB); +} + MachineInstr *AlphaRegisterInfo::foldMemoryOperand(MachineInstr *MI, unsigned OpNum, int FrameIndex) const { |