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| author | Andrew Lenharth <andrewl@lenharth.org> | 2006-09-20 20:08:52 +0000 |
|---|---|---|
| committer | Andrew Lenharth <andrewl@lenharth.org> | 2006-09-20 20:08:52 +0000 |
| commit | c459bbf0fdef4e9b074de8fee1728c08348c46dc (patch) | |
| tree | 1797a8d0b91b522139e5952448546e3c9084b074 /lib/Target/Alpha/AlphaLLRP.cpp | |
| parent | 4da1c82f724adba2832f79b3b49fc96c1467076d (diff) | |
Account for pseudo-ops correctly
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30548 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha/AlphaLLRP.cpp')
| -rw-r--r-- | lib/Target/Alpha/AlphaLLRP.cpp | 95 |
1 files changed, 51 insertions, 44 deletions
diff --git a/lib/Target/Alpha/AlphaLLRP.cpp b/lib/Target/Alpha/AlphaLLRP.cpp index 0ad86f4bb6..adae36f1cf 100644 --- a/lib/Target/Alpha/AlphaLLRP.cpp +++ b/lib/Target/Alpha/AlphaLLRP.cpp @@ -58,7 +58,6 @@ namespace { case Alpha::LDQ: case Alpha::LDL: case Alpha::LDWU: case Alpha::LDBU: case Alpha::LDT: case Alpha::LDS: - case Alpha::STQ: case Alpha::STL: case Alpha::STW: case Alpha::STB: case Alpha::STT: case Alpha::STS: @@ -89,49 +88,57 @@ namespace { Changed = true; nopintro += 2; count += 2; } else if (prev[2] - && prev[2]->getOperand(2).getReg() == - MI->getOperand(2).getReg() - && prev[2]->getOperand(1).getImmedValue() == - MI->getOperand(1).getImmedValue()) { - prev[0] = prev[1] = prev[2] = 0; - BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31) - .addReg(Alpha::R31); - BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31) - .addReg(Alpha::R31); - BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31) - .addReg(Alpha::R31); - Changed = true; nopintro += 3; - count += 3; - } - prev[0] = prev[1]; - prev[1] = prev[2]; - prev[2] = MI; - break; - } - //fall through - case Alpha::BR: - case Alpha::JMP: - ub = true; - //fall through - default: - prev[0] = prev[1]; - prev[1] = prev[2]; - prev[2] = 0; - break; - } - } - if (ub || AlignAll) { - //we can align stuff for free at this point - while (count % 4) { - BuildMI(MBB, MBB.end(), Alpha::BIS, 2, Alpha::R31) - .addReg(Alpha::R31).addReg(Alpha::R31); - ++count; - ++nopalign; - prev[0] = prev[1]; - prev[1] = prev[2]; - prev[2] = 0; - } - } + && prev[2]->getOperand(2).getReg() == + MI->getOperand(2).getReg() + && prev[2]->getOperand(1).getImmedValue() == + MI->getOperand(1).getImmedValue()) { + prev[0] = prev[1] = prev[2] = 0; + BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31) + .addReg(Alpha::R31); + BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31) + .addReg(Alpha::R31); + BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31) + .addReg(Alpha::R31); + Changed = true; nopintro += 3; + count += 3; + } + prev[0] = prev[1]; + prev[1] = prev[2]; + prev[2] = MI; + break; + } + prev[0] = prev[1]; + prev[1] = prev[2]; + prev[2] = 0; + break; + case Alpha::ALTENT: + case Alpha::MEMLABEL: + case Alpha::PCLABEL: + --count; + break; + case Alpha::BR: + case Alpha::JMP: + ub = true; + //fall through + default: + prev[0] = prev[1]; + prev[1] = prev[2]; + prev[2] = 0; + break; + } + } + if (ub || AlignAll) { + //we can align stuff for free at this point + while (count % 4) { + BuildMI(MBB, MBB.end(), Alpha::BIS, 2, Alpha::R31) + .addReg(Alpha::R31).addReg(Alpha::R31); + ++count; + ++nopalign; + prev[0] = prev[1]; + prev[1] = prev[2]; + prev[2] = 0; + } + } } return Changed; } |