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authorAndrew Lenharth <andrewl@lenharth.org>2006-10-31 23:46:56 +0000
committerAndrew Lenharth <andrewl@lenharth.org>2006-10-31 23:46:56 +0000
commit6bbf6b0b65f0458d50836dd575c5357f0c7a0bb4 (patch)
tree06fc457eb28c6707042fdae8359c01bea0e7f581 /lib/Target/Alpha/AlphaLLRP.cpp
parent0ccb500fa7a28baeb66754ff4a6950fa0e82617d (diff)
more shotenning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31331 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha/AlphaLLRP.cpp')
-rw-r--r--lib/Target/Alpha/AlphaLLRP.cpp14
1 files changed, 7 insertions, 7 deletions
diff --git a/lib/Target/Alpha/AlphaLLRP.cpp b/lib/Target/Alpha/AlphaLLRP.cpp
index adae36f1cf..eb2387740f 100644
--- a/lib/Target/Alpha/AlphaLLRP.cpp
+++ b/lib/Target/Alpha/AlphaLLRP.cpp
@@ -70,7 +70,7 @@ namespace {
prev[0] = prev[1];
prev[1] = prev[2];
prev[2] = 0;
- BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31)
+ BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31)
.addReg(Alpha::R31);
Changed = true; nopintro += 1;
count += 1;
@@ -81,9 +81,9 @@ namespace {
MI->getOperand(1).getImmedValue()) {
prev[0] = prev[2];
prev[1] = prev[2] = 0;
- BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31)
+ BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31)
.addReg(Alpha::R31);
- BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31)
+ BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31)
.addReg(Alpha::R31);
Changed = true; nopintro += 2;
count += 2;
@@ -93,11 +93,11 @@ namespace {
&& prev[2]->getOperand(1).getImmedValue() ==
MI->getOperand(1).getImmedValue()) {
prev[0] = prev[1] = prev[2] = 0;
- BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31)
+ BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31)
.addReg(Alpha::R31);
- BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31)
+ BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31)
.addReg(Alpha::R31);
- BuildMI(MBB, MI, Alpha::BIS, 2, Alpha::R31).addReg(Alpha::R31)
+ BuildMI(MBB, MI, Alpha::BISr, 2, Alpha::R31).addReg(Alpha::R31)
.addReg(Alpha::R31);
Changed = true; nopintro += 3;
count += 3;
@@ -130,7 +130,7 @@ namespace {
if (ub || AlignAll) {
//we can align stuff for free at this point
while (count % 4) {
- BuildMI(MBB, MBB.end(), Alpha::BIS, 2, Alpha::R31)
+ BuildMI(MBB, MBB.end(), Alpha::BISr, 2, Alpha::R31)
.addReg(Alpha::R31).addReg(Alpha::R31);
++count;
++nopalign;