diff options
| author | Dale Johannesen <dalej@apple.com> | 2009-02-13 02:30:42 +0000 |
|---|---|---|
| committer | Dale Johannesen <dalej@apple.com> | 2009-02-13 02:30:42 +0000 |
| commit | 01b36e6436a1d1d1dacdea777ae1dc7472f2fdd9 (patch) | |
| tree | 4101d8efd113d9cc969033f7aae3531d4c1702dd /lib/Target/Alpha/AlphaLLRP.cpp | |
| parent | bd9ef18f74a361e0ed630d373677c6fc0ce3cad9 (diff) | |
Remove non-DebugLoc versions of BuildMI from Alpha and Cell.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64433 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha/AlphaLLRP.cpp')
| -rw-r--r-- | lib/Target/Alpha/AlphaLLRP.cpp | 21 |
1 files changed, 11 insertions, 10 deletions
diff --git a/lib/Target/Alpha/AlphaLLRP.cpp b/lib/Target/Alpha/AlphaLLRP.cpp index 7a1b78497b..0c51bc554b 100644 --- a/lib/Target/Alpha/AlphaLLRP.cpp +++ b/lib/Target/Alpha/AlphaLLRP.cpp @@ -49,6 +49,7 @@ namespace { const TargetInstrInfo *TII = F.getTarget().getInstrInfo(); bool Changed = false; MachineInstr* prev[3] = {0,0,0}; + DebugLoc dl = DebugLoc::getUnknownLoc(); unsigned count = 0; for (MachineFunction::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI) { @@ -73,7 +74,7 @@ namespace { prev[0] = prev[1]; prev[1] = prev[2]; prev[2] = 0; - BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31) + BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31) .addReg(Alpha::R31) .addReg(Alpha::R31); Changed = true; nopintro += 1; @@ -85,10 +86,10 @@ namespace { MI->getOperand(1).getImm()) { prev[0] = prev[2]; prev[1] = prev[2] = 0; - BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31) + BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31) .addReg(Alpha::R31) .addReg(Alpha::R31); - BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31) + BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31) .addReg(Alpha::R31) .addReg(Alpha::R31); Changed = true; nopintro += 2; @@ -99,12 +100,12 @@ namespace { && prev[2]->getOperand(1).getImm() == MI->getOperand(1).getImm()) { prev[0] = prev[1] = prev[2] = 0; - BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31) - .addReg(Alpha::R31); - BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31) - .addReg(Alpha::R31); - BuildMI(MBB, MI, TII->get(Alpha::BISr), Alpha::R31).addReg(Alpha::R31) - .addReg(Alpha::R31); + BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31) + .addReg(Alpha::R31).addReg(Alpha::R31); + BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31) + .addReg(Alpha::R31).addReg(Alpha::R31); + BuildMI(MBB, MI, dl, TII->get(Alpha::BISr), Alpha::R31) + .addReg(Alpha::R31).addReg(Alpha::R31); Changed = true; nopintro += 3; count += 3; } @@ -136,7 +137,7 @@ namespace { if (ub || AlignAll) { //we can align stuff for free at this point while (count % 4) { - BuildMI(MBB, MBB.end(), TII->get(Alpha::BISr), Alpha::R31) + BuildMI(MBB, MBB.end(), dl, TII->get(Alpha::BISr), Alpha::R31) .addReg(Alpha::R31).addReg(Alpha::R31); ++count; ++nopalign; |