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authorJakob Stoklund Olesen <stoklund@2pi.dk>2010-07-16 22:35:46 +0000
committerJakob Stoklund Olesen <stoklund@2pi.dk>2010-07-16 22:35:46 +0000
commit78e6e009223a38739797629ca2d217acf86dda93 (patch)
tree75935c3cf8e6533ddac2b69d9f406335d165d772 /lib/Target/Alpha/AlphaInstrInfo.cpp
parent2aaa98da767ffd07e773a228bcae4adf65c49bc5 (diff)
Remove the isMoveInstr() hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108567 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha/AlphaInstrInfo.cpp')
-rw-r--r--lib/Target/Alpha/AlphaInstrInfo.cpp26
1 files changed, 0 insertions, 26 deletions
diff --git a/lib/Target/Alpha/AlphaInstrInfo.cpp b/lib/Target/Alpha/AlphaInstrInfo.cpp
index ad625a2694..5a2f5610fd 100644
--- a/lib/Target/Alpha/AlphaInstrInfo.cpp
+++ b/lib/Target/Alpha/AlphaInstrInfo.cpp
@@ -27,32 +27,6 @@ AlphaInstrInfo::AlphaInstrInfo()
RI(*this) { }
-bool AlphaInstrInfo::isMoveInstr(const MachineInstr& MI,
- unsigned& sourceReg, unsigned& destReg,
- unsigned& SrcSR, unsigned& DstSR) const {
- unsigned oc = MI.getOpcode();
- if (oc == Alpha::BISr ||
- oc == Alpha::CPYSS ||
- oc == Alpha::CPYST ||
- oc == Alpha::CPYSSt ||
- oc == Alpha::CPYSTs) {
- // or r1, r2, r2
- // cpys(s|t) r1 r2 r2
- assert(MI.getNumOperands() >= 3 &&
- MI.getOperand(0).isReg() &&
- MI.getOperand(1).isReg() &&
- MI.getOperand(2).isReg() &&
- "invalid Alpha BIS instruction!");
- if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
- sourceReg = MI.getOperand(1).getReg();
- destReg = MI.getOperand(0).getReg();
- SrcSR = DstSR = 0;
- return true;
- }
- }
- return false;
-}
-
unsigned
AlphaInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const {