diff options
| author | Andrew Lenharth <andrewl@lenharth.org> | 2005-11-09 19:17:08 +0000 |
|---|---|---|
| committer | Andrew Lenharth <andrewl@lenharth.org> | 2005-11-09 19:17:08 +0000 |
| commit | 5cefc5e64df314a148ff776634cca00c23a6f211 (patch) | |
| tree | cf73621975dc7560a5a4b8a5a6ce2f1dc468bd2a /lib/Target/Alpha/AlphaInstrInfo.cpp | |
| parent | 040c11c24e9f6c172eaf680e135d9bb466c284b2 (diff) | |
whatever. Intermediate patch to see what breaks. Seems ok.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24260 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha/AlphaInstrInfo.cpp')
| -rw-r--r-- | lib/Target/Alpha/AlphaInstrInfo.cpp | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/lib/Target/Alpha/AlphaInstrInfo.cpp b/lib/Target/Alpha/AlphaInstrInfo.cpp index ebbc4442d9..fc9ace7126 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.cpp +++ b/lib/Target/Alpha/AlphaInstrInfo.cpp @@ -26,7 +26,9 @@ bool AlphaInstrInfo::isMoveInstr(const MachineInstr& MI, unsigned& sourceReg, unsigned& destReg) const { MachineOpCode oc = MI.getOpcode(); - if (oc == Alpha::BIS || oc == Alpha::CPYS) { // or r1, r2, r2 // cpys r1 r2 r2 + if (oc == Alpha::BIS || oc == Alpha::CPYSS || oc == Alpha::CPYST) { + // or r1, r2, r2 + // cpys(s|t) r1 r2 r2 assert(MI.getNumOperands() == 3 && MI.getOperand(0).isRegister() && MI.getOperand(1).isRegister() && |