aboutsummaryrefslogtreecommitdiff
path: root/lib/Target/Alpha/AlphaInstrInfo.cpp
diff options
context:
space:
mode:
authorEvan Cheng <evan.cheng@apple.com>2009-01-20 19:12:24 +0000
committerEvan Cheng <evan.cheng@apple.com>2009-01-20 19:12:24 +0000
commit04ee5a1d9267e5e6fab8f088095fcb83c3c5cbd1 (patch)
tree83e8495f021a9e995df02cb9df4ed332e369e336 /lib/Target/Alpha/AlphaInstrInfo.cpp
parenta913f4fca947c195a675e04ba625fe9e67d1a865 (diff)
Change TargetInstrInfo::isMoveInstr to return source and destination sub-register indices as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62600 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha/AlphaInstrInfo.cpp')
-rw-r--r--lib/Target/Alpha/AlphaInstrInfo.cpp5
1 files changed, 3 insertions, 2 deletions
diff --git a/lib/Target/Alpha/AlphaInstrInfo.cpp b/lib/Target/Alpha/AlphaInstrInfo.cpp
index fa8224f113..2c7404d564 100644
--- a/lib/Target/Alpha/AlphaInstrInfo.cpp
+++ b/lib/Target/Alpha/AlphaInstrInfo.cpp
@@ -25,8 +25,8 @@ AlphaInstrInfo::AlphaInstrInfo()
bool AlphaInstrInfo::isMoveInstr(const MachineInstr& MI,
- unsigned& sourceReg,
- unsigned& destReg) const {
+ unsigned& sourceReg, unsigned& destReg,
+ unsigned& SrcSR, unsigned& DstSR) const {
unsigned oc = MI.getOpcode();
if (oc == Alpha::BISr ||
oc == Alpha::CPYSS ||
@@ -43,6 +43,7 @@ bool AlphaInstrInfo::isMoveInstr(const MachineInstr& MI,
if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
sourceReg = MI.getOperand(1).getReg();
destReg = MI.getOperand(0).getReg();
+ SrcSR = DstSR = 0;
return true;
}
}