diff options
| author | Dale Johannesen <dalej@apple.com> | 2009-02-13 02:30:42 +0000 |
|---|---|---|
| committer | Dale Johannesen <dalej@apple.com> | 2009-02-13 02:30:42 +0000 |
| commit | 01b36e6436a1d1d1dacdea777ae1dc7472f2fdd9 (patch) | |
| tree | 4101d8efd113d9cc969033f7aae3531d4c1702dd /lib/Target/Alpha/AlphaInstrInfo.cpp | |
| parent | bd9ef18f74a361e0ed630d373677c6fc0ce3cad9 (diff) | |
Remove non-DebugLoc versions of BuildMI from Alpha and Cell.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64433 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/Alpha/AlphaInstrInfo.cpp')
| -rw-r--r-- | lib/Target/Alpha/AlphaInstrInfo.cpp | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/lib/Target/Alpha/AlphaInstrInfo.cpp b/lib/Target/Alpha/AlphaInstrInfo.cpp index 42dc448021..73e9b7b2d5 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.cpp +++ b/lib/Target/Alpha/AlphaInstrInfo.cpp @@ -108,6 +108,8 @@ unsigned AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond) const { + // FIXME this should probably have a DebugLoc argument + DebugLoc dl = DebugLoc::getUnknownLoc(); assert(TBB && "InsertBranch must not be told to insert a fallthrough"); assert((Cond.size() == 2 || Cond.size() == 0) && "Alpha branch conditions have two components!"); @@ -115,25 +117,25 @@ unsigned AlphaInstrInfo::InsertBranch(MachineBasicBlock &MBB, // One-way branch. if (FBB == 0) { if (Cond.empty()) // Unconditional branch - BuildMI(&MBB, get(Alpha::BR)).addMBB(TBB); + BuildMI(&MBB, dl, get(Alpha::BR)).addMBB(TBB); else // Conditional branch if (isAlphaIntCondCode(Cond[0].getImm())) - BuildMI(&MBB, get(Alpha::COND_BRANCH_I)) + BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_I)) .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); else - BuildMI(&MBB, get(Alpha::COND_BRANCH_F)) + BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_F)) .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); return 1; } // Two-way Conditional Branch. if (isAlphaIntCondCode(Cond[0].getImm())) - BuildMI(&MBB, get(Alpha::COND_BRANCH_I)) + BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_I)) .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); else - BuildMI(&MBB, get(Alpha::COND_BRANCH_F)) + BuildMI(&MBB, dl, get(Alpha::COND_BRANCH_F)) .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); - BuildMI(&MBB, get(Alpha::BR)).addMBB(FBB); + BuildMI(&MBB, dl, get(Alpha::BR)).addMBB(FBB); return 2; } |